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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2014-10-29 05:32:35 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-07 12:41:45 -0500
commit3fb37703683543725dec3d8bc5c5b3a930325d04 (patch)
tree752ab87fe70f43939a8c285f19af74d6df2faefb /drivers/gpu/drm/i915/intel_display.c
parent797d02592304b15359f407bd0e52fa5143cb4c9f (diff)
drm/i915: Covert ILK-IVB to choose DPLLS before disabling CRTCs
Use the infrastructure added in a previous patch to choose shared DPLLs and calculate clocks before touching the hardware. v2: Don't set mode_set hooks since dev_priv is kzalloc()'d (Ville) Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c13
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e4bff0b8740f..ee5eba78334d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7418,9 +7418,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7418 return dpll | DPLL_VCO_ENABLE; 7418 return dpll | DPLL_VCO_ENABLE;
7419} 7419}
7420 7420
7421static int ironlake_crtc_mode_set(struct intel_crtc *crtc, 7421static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7422 int x, int y,
7423 struct drm_framebuffer *fb)
7424{ 7422{
7425 struct drm_device *dev = crtc->base.dev; 7423 struct drm_device *dev = crtc->base.dev;
7426 intel_clock_t clock, reduced_clock; 7424 intel_clock_t clock, reduced_clock;
@@ -7466,17 +7464,13 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
7466 else 7464 else
7467 crtc->new_config->dpll_hw_state.fp1 = fp; 7465 crtc->new_config->dpll_hw_state.fp1 = fp;
7468 7466
7469 if (intel_crtc_to_shared_dpll(crtc))
7470 intel_put_shared_dpll(crtc);
7471
7472 pll = intel_get_shared_dpll(crtc); 7467 pll = intel_get_shared_dpll(crtc);
7473 if (pll == NULL) { 7468 if (pll == NULL) {
7474 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 7469 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7475 pipe_name(crtc->pipe)); 7470 pipe_name(crtc->pipe));
7476 return -EINVAL; 7471 return -EINVAL;
7477 } 7472 }
7478 } else 7473 }
7479 intel_put_shared_dpll(crtc);
7480 7474
7481 if (is_lvds && has_reduced_clock && i915.powersave) 7475 if (is_lvds && has_reduced_clock && i915.powersave)
7482 crtc->lowfreq_avail = true; 7476 crtc->lowfreq_avail = true;
@@ -12480,7 +12474,8 @@ static void intel_init_display(struct drm_device *dev)
12480 } else if (HAS_PCH_SPLIT(dev)) { 12474 } else if (HAS_PCH_SPLIT(dev)) {
12481 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; 12475 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12482 dev_priv->display.get_plane_config = ironlake_get_plane_config; 12476 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12483 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 12477 dev_priv->display.crtc_compute_clock =
12478 ironlake_crtc_compute_clock;
12484 dev_priv->display.crtc_enable = ironlake_crtc_enable; 12479 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12485 dev_priv->display.crtc_disable = ironlake_crtc_disable; 12480 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12486 dev_priv->display.off = ironlake_crtc_off; 12481 dev_priv->display.off = ironlake_crtc_off;