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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-24 12:07:48 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-24 12:17:12 -0400
commit398b7a1b882a655ee84bd985f6c2ba89082404ae (patch)
tree5eb9284a87ee2a45a10809cfbe3a66fea6ea53ae /drivers/gpu/drm/i915/intel_display.c
parent57df2ae9df6e335a98969cac5aafb09c4de10bb2 (diff)
parent979570e02981d4a8fc20b3cc8fd651856c98ee9d (diff)
Merge tag 'v3.6-rc7' into drm-intel-next-queued
Manual backmerge of -rc7 to resolve a silent conflict leading to compile failure in drivers/gpu/drm/i915/intel_hdmi.c. This is due to the bugfix in -rc7: commit b98b60167279df3acac9422c3c9820d9ebbcf9fb Author: Wang Xingchao <xingchao.wang@intel.com> Date: Thu Sep 13 07:43:22 2012 +0800 drm/i915: HDMI - Clear Audio Enable bit for Hot Plug Since this code moved around a lot in -next git put that snippet at the wrong spot. I've tried to fix this by making the conflict explicit by merging a version for next with: commit 3cce574f0190dd149472059fb69267cf83d290f9 Author: Wang Xingchao <xingchao.wang@intel.com> Date: Thu Sep 13 11:19:00 2012 +0800 drm/i915: HDMI - Clear Audio Enable bit for Hot Plug unconditionally But that failed to solve the entire problem. To avoid pushing out further -nightly branch to our QA where this is broken, do the backmerge and manually add the stuff git adds to -next from the patch in -fixes. Note that this doesn't show up in git's merge diff (and hence is also not handled by git rerere), which adds to the reasons why I'd like to fix this with a verbose backmerge. The git merge diff only shows a bunch of trivial conflicts of the "code changed in lines next to each another" kind. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 947c97d427cc..6f5aafa1b633 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1376,7 +1376,8 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe)); 1377 reg, pipe_name(pipe));
1378 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1380 && (val & DP_PIPEB_SELECT),
1380 "IBX PCH dp port still using transcoder B\n"); 1381 "IBX PCH dp port still using transcoder B\n");
1381} 1382}
1382 1383
@@ -1388,7 +1389,8 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe)); 1390 reg, pipe_name(pipe));
1390 1391
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT), 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1393 && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n"); 1394 "IBX PCH hdmi port still using transcoder B\n");
1393} 1395}
1394 1396
@@ -4229,12 +4231,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
4229 POSTING_READ(DPLL(pipe)); 4231 POSTING_READ(DPLL(pipe));
4230 udelay(150); 4232 udelay(150);
4231 4233
4232 I915_WRITE(DPLL(pipe), dpll);
4233
4234 /* Wait for the clocks to stabilize. */
4235 POSTING_READ(DPLL(pipe));
4236 udelay(150);
4237
4238 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 4234 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4239 * This is an exception to the general rule that mode_set doesn't turn 4235 * This is an exception to the general rule that mode_set doesn't turn
4240 * things on. 4236 * things on.
@@ -4242,6 +4238,12 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 4238 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4243 intel_update_lvds(crtc, clock, adjusted_mode); 4239 intel_update_lvds(crtc, clock, adjusted_mode);
4244 4240
4241 I915_WRITE(DPLL(pipe), dpll);
4242
4243 /* Wait for the clocks to stabilize. */
4244 POSTING_READ(DPLL(pipe));
4245 udelay(150);
4246
4245 /* The pixel multiplier can only be updated once the 4247 /* The pixel multiplier can only be updated once the
4246 * DPLL is enabled and the clocks are stable. 4248 * DPLL is enabled and the clocks are stable.
4247 * 4249 *