drm/i915: Split chv_update_pll() apart

Split chv_update_pll() into two parts ala:
 commit bdd4b6a655749970cc632aafc5fd596c07b60b1c
 Author: Daniel Vetter <daniel.vetter@ffwll.ch>
 Date:   Thu Apr 24 23:55:11 2014 +0200

    drm/i915: Extract vlv_prepare_pll

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 19 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6ca53b372a4c..60ba6962026b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -100,6 +100,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 static void vlv_prepare_pll(struct intel_crtc *crtc);
+static void chv_prepare_pll(struct intel_crtc *crtc);
 
 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
 {
@@ -4642,8 +4643,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
 
         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
 
-        if (!is_dsi && !IS_CHERRYVIEW(dev))
-                vlv_prepare_pll(intel_crtc);
+        if (!is_dsi) {
+                if (IS_CHERRYVIEW(dev))
+                        chv_prepare_pll(intel_crtc);
+                else
+                        vlv_prepare_pll(intel_crtc);
+        }
 
         /* Set up the display plane register */
         dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -5692,6 +5697,18 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
 
 static void chv_update_pll(struct intel_crtc *crtc)
 {
+        crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
+                DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
+                DPLL_VCO_ENABLE;
+        if (crtc->pipe != PIPE_A)
+                crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+        crtc->config.dpll_hw_state.dpll_md =
+                (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+}
+
+static void chv_prepare_pll(struct intel_crtc *crtc)
+{
         struct drm_device *dev = crtc->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         int pipe = crtc->pipe;
@@ -5701,15 +5718,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
         int refclk;
 
-        crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
-                DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
-                DPLL_VCO_ENABLE;
-        if (pipe != PIPE_A)
-                crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
-        crtc->config.dpll_hw_state.dpll_md =
-                (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
-
         bestn = crtc->config.dpll.n;
         bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
         bestm1 = crtc->config.dpll.m1;