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authorZhao Yakui <yakui.zhao@intel.com>2010-01-04 03:29:32 -0500
committerEric Anholt <eric@anholt.net>2010-01-06 12:40:13 -0500
commite5a95eb778690bc864eb330202d2c1b974caaeb4 (patch)
treeac6e92b9a488812ab46e1819f184d0d1cdc9b18e /drivers/gpu/drm/i915/intel_display.c
parent8faf3b317471179c02db339aa80955a2e88c036d (diff)
drm/i915: Select the correct BPC for LVDS on Ironlake
Select the correct BPC for LVDS on Ironlake. If it is 18-bit LVDS panel, the BPC will be 6. When it is 24-bit LVDS panel, the BPC will 8. At the same time the BPC will be 8 when the output device is CRT/HDMI/DP. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63e8e9fd6793..5e2159b59920 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2993,6 +2993,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2993 2993
2994 /* determine panel color depth */ 2994 /* determine panel color depth */
2995 temp = I915_READ(pipeconf_reg); 2995 temp = I915_READ(pipeconf_reg);
2996 temp &= ~PIPE_BPC_MASK;
2997 if (is_lvds) {
2998 int lvds_reg = I915_READ(PCH_LVDS);
2999 /* the BPC will be 6 if it is 18-bit LVDS panel */
3000 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3001 temp |= PIPE_8BPC;
3002 else
3003 temp |= PIPE_6BPC;
3004 } else
3005 temp |= PIPE_8BPC;
3006 I915_WRITE(pipeconf_reg, temp);
3007 I915_READ(pipeconf_reg);
2996 3008
2997 switch (temp & PIPE_BPC_MASK) { 3009 switch (temp & PIPE_BPC_MASK) {
2998 case PIPE_8BPC: 3010 case PIPE_8BPC: