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authorDaniel Vetter <daniel.vetter@ffwll.ch>2010-11-04 12:11:09 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-04 15:02:03 -0400
commit75e9e9158f38e5cb21eff23b30bafa6f32e0a606 (patch)
treec52330f275112d47762a0ef0bde1efb5a82e748f /drivers/gpu/drm/i915/intel_display.c
parent818f2a3cc34b0673dccd4188ce4a1862d9d90127 (diff)
drm/i915: kill mappable/fenceable disdinction
a00b10c360b35d6431a "Only enforce fence limits inside the GTT" also added a fenceable/mappable disdinction when binding/pinning buffers. This only complicates the code with no pratical gain: - In execbuffer this matters on for g33/pineview, as this is the only chip that needs fences and has an unmappable gtt area. But fences are only possible in the mappable part of the gtt, so need_fence implies need_mappable. And need_mappable is only set independantly with relocations which implies (for sane userspace) that the buffer is untiled. - The overlay code is only really used on i8xx, which doesn't have unmappable gtt. And it doesn't support tiled buffers, currently. - For all other buffers it's a bug to pass in a tiled bo. In short, this disdinction doesn't have any practical gain. I've also reverted mapping the overlay and context pages as possibly unmappable. It's not worth being overtly clever here, all the big gains from unmappable are for execbuf bos. Also add a comment for a clever optimization that confused me while reading the original patch by Chris Wilson. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a2cd579eb9b2..77b34942dc91 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1461,8 +1461,7 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev,
1461 BUG(); 1461 BUG();
1462 } 1462 }
1463 1463
1464 ret = i915_gem_object_pin(obj, alignment, true, 1464 ret = i915_gem_object_pin(obj, alignment, true);
1465 obj_priv->tiling_mode);
1466 if (ret) 1465 if (ret)
1467 return ret; 1466 return ret;
1468 1467
@@ -4367,7 +4366,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4367 /* we only need to pin inside GTT if cursor is non-phy */ 4366 /* we only need to pin inside GTT if cursor is non-phy */
4368 mutex_lock(&dev->struct_mutex); 4367 mutex_lock(&dev->struct_mutex);
4369 if (!dev_priv->info->cursor_needs_physical) { 4368 if (!dev_priv->info->cursor_needs_physical) {
4370 ret = i915_gem_object_pin(bo, PAGE_SIZE, true, false); 4369 ret = i915_gem_object_pin(bo, PAGE_SIZE, true);
4371 if (ret) { 4370 if (ret) {
4372 DRM_ERROR("failed to pin cursor bo\n"); 4371 DRM_ERROR("failed to pin cursor bo\n");
4373 goto fail_locked; 4372 goto fail_locked;
@@ -5531,7 +5530,7 @@ intel_alloc_context_page(struct drm_device *dev)
5531 } 5530 }
5532 5531
5533 mutex_lock(&dev->struct_mutex); 5532 mutex_lock(&dev->struct_mutex);
5534 ret = i915_gem_object_pin(ctx, 4096, false, false); 5533 ret = i915_gem_object_pin(ctx, 4096, true);
5535 if (ret) { 5534 if (ret) {
5536 DRM_ERROR("failed to pin power context: %d\n", ret); 5535 DRM_ERROR("failed to pin power context: %d\n", ret);
5537 goto err_unref; 5536 goto err_unref;