diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-25 05:05:17 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-08 05:23:27 -0400 |
commit | 6c9547ff354d867318d78094aa8e9cf5218851e2 (patch) | |
tree | 88907cc36767faa27ea8ea9171d4febac1216de6 /drivers/gpu/drm/i915/intel_display.c | |
parent | 57cd6508da65adabcb14be6ba3b9370d750b647d (diff) |
drm/i915/sdvo: Preserve pixel-multiplier
Store the pixel-multiplier on the adjusted mode and avoid modifying the
requested mode.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index adce19304eee..120a9c0c2da6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3519,7 +3519,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3519 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; | 3519 | int trans_dpll_sel = (pipe == 0) ? 0 : 1; |
3520 | int lvds_reg = LVDS; | 3520 | int lvds_reg = LVDS; |
3521 | u32 temp; | 3521 | u32 temp; |
3522 | int sdvo_pixel_multiply; | ||
3523 | int target_clock; | 3522 | int target_clock; |
3524 | 3523 | ||
3525 | drm_vblank_pre_modeset(dev, pipe); | 3524 | drm_vblank_pre_modeset(dev, pipe); |
@@ -3770,12 +3769,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3770 | else | 3769 | else |
3771 | dpll |= DPLLB_MODE_DAC_SERIAL; | 3770 | dpll |= DPLLB_MODE_DAC_SERIAL; |
3772 | if (is_sdvo) { | 3771 | if (is_sdvo) { |
3772 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | ||
3773 | if (pixel_multiplier > 1) { | ||
3774 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | ||
3775 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | ||
3776 | else if (HAS_PCH_SPLIT(dev)) | ||
3777 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | ||
3778 | } | ||
3773 | dpll |= DPLL_DVO_HIGH_SPEED; | 3779 | dpll |= DPLL_DVO_HIGH_SPEED; |
3774 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | ||
3775 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | ||
3776 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | ||
3777 | else if (HAS_PCH_SPLIT(dev)) | ||
3778 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | ||
3779 | } | 3780 | } |
3780 | if (is_dp) | 3781 | if (is_dp) |
3781 | dpll |= DPLL_DVO_HIGH_SPEED; | 3782 | dpll |= DPLL_DVO_HIGH_SPEED; |
@@ -3982,9 +3983,15 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3982 | 3983 | ||
3983 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { | 3984 | if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) { |
3984 | if (is_sdvo) { | 3985 | if (is_sdvo) { |
3985 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | 3986 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
3986 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | | 3987 | if (pixel_multiplier > 1) |
3987 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | 3988 | pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
3989 | else | ||
3990 | pixel_multiplier = 0; | ||
3991 | |||
3992 | I915_WRITE(dpll_md_reg, | ||
3993 | (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | | ||
3994 | pixel_multiplier); | ||
3988 | } else | 3995 | } else |
3989 | I915_WRITE(dpll_md_reg, 0); | 3996 | I915_WRITE(dpll_md_reg, 0); |
3990 | } else { | 3997 | } else { |