diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-02-22 09:20:07 -0500 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-02-22 09:20:18 -0500 |
commit | 2daa79ec2126f8e710391e9d8e8f0d31d7c91d5f (patch) | |
tree | ab89c74c09c2986fa01c25ad8e45989a48a18899 /drivers/gpu/drm/i915/intel_display.c | |
parent | 7dae8c5209147ad06d424928a5f1ec45caa87691 (diff) | |
parent | 678a0222edc9da43a22145d68647500ee85e6c04 (diff) |
Merge branch 'lpc32xx/drivers' into next/drivers
* lpc32xx/drivers: (566 commits)
ARM: LPC32xx: ADC support for mach-lpc32xx
Includes an update to Linux 3.3-rc4
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b3b51c43dad0..00fbff5ddd81 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1872,7 +1872,7 @@ static void intel_update_fbc(struct drm_device *dev) | |||
1872 | if (enable_fbc < 0) { | 1872 | if (enable_fbc < 0) { |
1873 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | 1873 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
1874 | enable_fbc = 1; | 1874 | enable_fbc = 1; |
1875 | if (INTEL_INFO(dev)->gen <= 5) | 1875 | if (INTEL_INFO(dev)->gen <= 6) |
1876 | enable_fbc = 0; | 1876 | enable_fbc = 0; |
1877 | } | 1877 | } |
1878 | if (!enable_fbc) { | 1878 | if (!enable_fbc) { |
@@ -5307,6 +5307,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, | |||
5307 | } | 5307 | } |
5308 | } | 5308 | } |
5309 | 5309 | ||
5310 | pipeconf &= ~PIPECONF_INTERLACE_MASK; | ||
5310 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | 5311 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5311 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | 5312 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5312 | /* the chip adds 2 halflines automatically */ | 5313 | /* the chip adds 2 halflines automatically */ |
@@ -5317,7 +5318,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, | |||
5317 | adjusted_mode->crtc_vsync_end -= 1; | 5318 | adjusted_mode->crtc_vsync_end -= 1; |
5318 | adjusted_mode->crtc_vsync_start -= 1; | 5319 | adjusted_mode->crtc_vsync_start -= 1; |
5319 | } else | 5320 | } else |
5320 | pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */ | 5321 | pipeconf |= PIPECONF_PROGRESSIVE; |
5321 | 5322 | ||
5322 | I915_WRITE(HTOTAL(pipe), | 5323 | I915_WRITE(HTOTAL(pipe), |
5323 | (adjusted_mode->crtc_hdisplay - 1) | | 5324 | (adjusted_mode->crtc_hdisplay - 1) | |
@@ -5902,6 +5903,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |||
5902 | } | 5903 | } |
5903 | } | 5904 | } |
5904 | 5905 | ||
5906 | pipeconf &= ~PIPECONF_INTERLACE_MASK; | ||
5905 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | 5907 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5906 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | 5908 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5907 | /* the chip adds 2 halflines automatically */ | 5909 | /* the chip adds 2 halflines automatically */ |
@@ -5912,7 +5914,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |||
5912 | adjusted_mode->crtc_vsync_end -= 1; | 5914 | adjusted_mode->crtc_vsync_end -= 1; |
5913 | adjusted_mode->crtc_vsync_start -= 1; | 5915 | adjusted_mode->crtc_vsync_start -= 1; |
5914 | } else | 5916 | } else |
5915 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | 5917 | pipeconf |= PIPECONF_PROGRESSIVE; |
5916 | 5918 | ||
5917 | I915_WRITE(HTOTAL(pipe), | 5919 | I915_WRITE(HTOTAL(pipe), |
5918 | (adjusted_mode->crtc_hdisplay - 1) | | 5920 | (adjusted_mode->crtc_hdisplay - 1) | |