diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-21 09:57:17 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-10-21 14:08:39 -0400 |
commit | f00a3ddf91d596bece5fa31e8ce2e8a3b4c0623b (patch) | |
tree | cae4beb61a2ae44ffa6d892bbd207b4022094dc2 /drivers/gpu/drm/i915/intel_display.c | |
parent | 549f7365820a212a1cfd0871d377b1ad0d1e5723 (diff) |
drm/i915: IS_IRONLAKE is synonymous with gen == 5
So remove the redundant bit in the capabilities block and
s/IS_IRONLAKE/IS_GEN5/.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index cda36b348fe8..e031d82381e5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -4152,7 +4152,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
4152 | 4152 | ||
4153 | intel_wait_for_vblank(dev, pipe); | 4153 | intel_wait_for_vblank(dev, pipe); |
4154 | 4154 | ||
4155 | if (IS_IRONLAKE(dev)) { | 4155 | if (IS_GEN5(dev)) { |
4156 | /* enable address swizzle for tiling buffer */ | 4156 | /* enable address swizzle for tiling buffer */ |
4157 | temp = I915_READ(DISP_ARB_CTL); | 4157 | temp = I915_READ(DISP_ARB_CTL); |
4158 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | 4158 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); |
@@ -5736,7 +5736,7 @@ void intel_init_clock_gating(struct drm_device *dev) | |||
5736 | if (HAS_PCH_SPLIT(dev)) { | 5736 | if (HAS_PCH_SPLIT(dev)) { |
5737 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | 5737 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
5738 | 5738 | ||
5739 | if (IS_IRONLAKE(dev)) { | 5739 | if (IS_GEN5(dev)) { |
5740 | /* Required for FBC */ | 5740 | /* Required for FBC */ |
5741 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | 5741 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; |
5742 | /* Required for CxSR */ | 5742 | /* Required for CxSR */ |
@@ -5763,7 +5763,7 @@ void intel_init_clock_gating(struct drm_device *dev) | |||
5763 | * The bit 5 of 0x42020 | 5763 | * The bit 5 of 0x42020 |
5764 | * The bit 15 of 0x45000 | 5764 | * The bit 15 of 0x45000 |
5765 | */ | 5765 | */ |
5766 | if (IS_IRONLAKE(dev)) { | 5766 | if (IS_GEN5(dev)) { |
5767 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 5767 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5768 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | 5768 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
5769 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | 5769 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
@@ -5939,7 +5939,7 @@ static void intel_init_display(struct drm_device *dev) | |||
5939 | 5939 | ||
5940 | /* For FIFO watermark updates */ | 5940 | /* For FIFO watermark updates */ |
5941 | if (HAS_PCH_SPLIT(dev)) { | 5941 | if (HAS_PCH_SPLIT(dev)) { |
5942 | if (IS_IRONLAKE(dev)) { | 5942 | if (IS_GEN5(dev)) { |
5943 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) | 5943 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
5944 | dev_priv->display.update_wm = ironlake_update_wm; | 5944 | dev_priv->display.update_wm = ironlake_update_wm; |
5945 | else { | 5945 | else { |