drm/i915: add dynamic performance control support for Ironlake

Ironlake (and 965GM, which this patch doesn't support) supports a
hardware performance and power management feature that allows it to
adjust to changes in GPU load over time with software help.  The goal
if this is to maximize performance/power for a given workload.

This patch enables that feature, which is also a requirement for
supporting Intelligent Power Sharing, a feature which allows for
dynamic budgeting of power between the CPU and GPU in Arrandale
platforms.

Tested-by: ykzhao <yakui.zhao@intel.com>
[anholt: Resolved against the irq handler loop removal]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a3b90c9561dc..2c346645acfa 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -682,6 +682,7 @@ void i915_restore_display(struct drm_device *dev)
                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
                 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
+                I915_WRITE(RSTDBYCTL, dev_priv->saveRSTDBYCTL);
         } else {
                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
                 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
@@ -745,11 +746,15 @@ int i915_save_state(struct drm_device *dev)
                 dev_priv->saveGTIMR = I915_READ(GTIMR);
                 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
                 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
+                dev_priv->saveRSTDBYCTL = I915_READ(RSTDBYCTL);
         } else {
                 dev_priv->saveIER = I915_READ(IER);
                 dev_priv->saveIMR = I915_READ(IMR);
         }
 
+        if (IS_IRONLAKE_M(dev))
+                ironlake_disable_drps(dev);
+
         /* Cache mode state */
         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
@@ -820,6 +825,9 @@ int i915_restore_state(struct drm_device *dev)
         /* Clock gating state */
         intel_init_clock_gating(dev);
 
+        if (IS_IRONLAKE_M(dev))
+                ironlake_enable_drps(dev);
+
         /* Cache mode state */
         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);