drm/i915: restore render clock gating on resume

Rather than restoring just a few clock gating registers on resume,
just reinitialize the whole thing.

Signed-off-by: Andy Lutomirski <luto@mit.edu>
[anholt: Fixed up for RC6 support landed since the patch was written]
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 1 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 402a7eb2922c..00f6d97c7cc5 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -722,10 +722,6 @@ int i915_save_state(struct drm_device *dev)
                 dev_priv->saveIMR = I915_READ(IMR);
         }
 
-        /* Clock gating state */
-        dev_priv->saveD_STATE = I915_READ(D_STATE);
-        dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
-
         /* Cache mode state */
         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 
@@ -800,8 +796,7 @@ int i915_restore_state(struct drm_device *dev)
         }
 
         /* Clock gating state */
-        I915_WRITE (D_STATE, dev_priv->saveD_STATE);
-        I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
+        intel_init_clock_gating(dev);
 
         /* Cache mode state */
         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);