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authorAdam Jackson <ajax@redhat.com>2009-12-03 17:14:42 -0500
committerEric Anholt <eric@anholt.net>2009-12-07 17:55:56 -0500
commitf2b115e69d46344ae7afcaad5823496d2a0d8650 (patch)
tree8bf56f7d43e3462a26088317bad04f04b676d26c /drivers/gpu/drm/i915/i915_suspend.c
parent107f517b8f2a9d5858e640bc046606b1cff14bb5 (diff)
drm/i915: Fix product names and #defines
IGD* isn't a useful name. Replace with the codenames, as sourced from pci.ids. Signed-off-by: Adam Jackson <ajax@redhat.com> [anholt: Fixed up for merge with pineview/ironlake changes] Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_suspend.c')
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index c5a6df93e1b6..402a7eb2922c 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,7 +34,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (IS_IGDNG(dev)) { 37 if (IS_IRONLAKE(dev)) {
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
39 } else { 39 } else {
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
@@ -53,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
53 if (!i915_pipe_enabled(dev, pipe)) 53 if (!i915_pipe_enabled(dev, pipe))
54 return; 54 return;
55 55
56 if (IS_IGDNG(dev)) 56 if (IS_IRONLAKE(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58 58
59 if (pipe == PIPE_A) 59 if (pipe == PIPE_A)
@@ -75,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
75 if (!i915_pipe_enabled(dev, pipe)) 75 if (!i915_pipe_enabled(dev, pipe))
76 return; 76 return;
77 77
78 if (IS_IGDNG(dev)) 78 if (IS_IRONLAKE(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80 80
81 if (pipe == PIPE_A) 81 if (pipe == PIPE_A)
@@ -242,7 +242,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
242 /* Pipe & plane A info */ 242 /* Pipe & plane A info */
243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
245 if (IS_IGDNG(dev)) { 245 if (IS_IRONLAKE(dev)) {
246 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 246 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
247 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 247 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
248 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 248 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
@@ -251,7 +251,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
251 dev_priv->saveFPA1 = I915_READ(FPA1); 251 dev_priv->saveFPA1 = I915_READ(FPA1);
252 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 252 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
253 } 253 }
254 if (IS_I965G(dev) && !IS_IGDNG(dev)) 254 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
255 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 255 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
256 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 256 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
257 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 257 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
@@ -259,10 +259,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
259 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 259 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
260 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 260 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
261 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 261 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
262 if (!IS_IGDNG(dev)) 262 if (!IS_IRONLAKE(dev))
263 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 263 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
264 264
265 if (IS_IGDNG(dev)) { 265 if (IS_IRONLAKE(dev)) {
266 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL); 266 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
267 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL); 267 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
268 268
@@ -293,7 +293,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
293 /* Pipe & plane B info */ 293 /* Pipe & plane B info */
294 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 294 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
295 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 295 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
296 if (IS_IGDNG(dev)) { 296 if (IS_IRONLAKE(dev)) {
297 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 297 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
298 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 298 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
299 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 299 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
@@ -302,7 +302,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
302 dev_priv->saveFPB1 = I915_READ(FPB1); 302 dev_priv->saveFPB1 = I915_READ(FPB1);
303 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 303 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
304 } 304 }
305 if (IS_I965G(dev) && !IS_IGDNG(dev)) 305 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
306 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 306 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
307 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 307 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
308 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 308 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
@@ -310,10 +310,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
310 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 310 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
311 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 311 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
312 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 312 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
313 if (!IS_IGDNG(dev)) 313 if (!IS_IRONLAKE(dev))
314 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 314 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
315 315
316 if (IS_IGDNG(dev)) { 316 if (IS_IRONLAKE(dev)) {
317 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL); 317 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
318 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL); 318 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
319 319
@@ -352,7 +352,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
352 if (drm_core_check_feature(dev, DRIVER_MODESET)) 352 if (drm_core_check_feature(dev, DRIVER_MODESET))
353 return; 353 return;
354 354
355 if (IS_IGDNG(dev)) { 355 if (IS_IRONLAKE(dev)) {
356 dpll_a_reg = PCH_DPLL_A; 356 dpll_a_reg = PCH_DPLL_A;
357 dpll_b_reg = PCH_DPLL_B; 357 dpll_b_reg = PCH_DPLL_B;
358 fpa0_reg = PCH_FPA0; 358 fpa0_reg = PCH_FPA0;
@@ -380,7 +380,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
380 /* Actually enable it */ 380 /* Actually enable it */
381 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 381 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
382 DRM_UDELAY(150); 382 DRM_UDELAY(150);
383 if (IS_I965G(dev) && !IS_IGDNG(dev)) 383 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
384 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 384 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
385 DRM_UDELAY(150); 385 DRM_UDELAY(150);
386 386
@@ -391,10 +391,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
391 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 391 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
392 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 392 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
393 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 393 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
394 if (!IS_IGDNG(dev)) 394 if (!IS_IRONLAKE(dev))
395 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 395 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
396 396
397 if (IS_IGDNG(dev)) { 397 if (IS_IRONLAKE(dev)) {
398 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL); 398 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
399 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL); 399 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
400 400
@@ -450,10 +450,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
453 if (!IS_IGDNG(dev)) 453 if (!IS_IRONLAKE(dev))
454 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 454 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
455 455
456 if (IS_IGDNG(dev)) { 456 if (IS_IRONLAKE(dev)) {
457 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL); 457 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
458 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL); 458 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
459 459
@@ -512,14 +512,14 @@ void i915_save_display(struct drm_device *dev)
512 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 512 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
513 513
514 /* CRT state */ 514 /* CRT state */
515 if (IS_IGDNG(dev)) { 515 if (IS_IRONLAKE(dev)) {
516 dev_priv->saveADPA = I915_READ(PCH_ADPA); 516 dev_priv->saveADPA = I915_READ(PCH_ADPA);
517 } else { 517 } else {
518 dev_priv->saveADPA = I915_READ(ADPA); 518 dev_priv->saveADPA = I915_READ(ADPA);
519 } 519 }
520 520
521 /* LVDS state */ 521 /* LVDS state */
522 if (IS_IGDNG(dev)) { 522 if (IS_IRONLAKE(dev)) {
523 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 523 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
524 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 524 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
525 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); 525 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
@@ -537,10 +537,10 @@ void i915_save_display(struct drm_device *dev)
537 dev_priv->saveLVDS = I915_READ(LVDS); 537 dev_priv->saveLVDS = I915_READ(LVDS);
538 } 538 }
539 539
540 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) 540 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev))
541 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 541 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
542 542
543 if (IS_IGDNG(dev)) { 543 if (IS_IRONLAKE(dev)) {
544 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 544 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
545 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 545 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
546 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); 546 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
@@ -580,7 +580,7 @@ void i915_save_display(struct drm_device *dev)
580 dev_priv->saveVGA0 = I915_READ(VGA0); 580 dev_priv->saveVGA0 = I915_READ(VGA0);
581 dev_priv->saveVGA1 = I915_READ(VGA1); 581 dev_priv->saveVGA1 = I915_READ(VGA1);
582 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 582 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
583 if (IS_IGDNG(dev)) 583 if (IS_IRONLAKE(dev))
584 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 584 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
585 else 585 else
586 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 586 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
@@ -622,24 +622,24 @@ void i915_restore_display(struct drm_device *dev)
622 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 622 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
623 623
624 /* CRT state */ 624 /* CRT state */
625 if (IS_IGDNG(dev)) 625 if (IS_IRONLAKE(dev))
626 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 626 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
627 else 627 else
628 I915_WRITE(ADPA, dev_priv->saveADPA); 628 I915_WRITE(ADPA, dev_priv->saveADPA);
629 629
630 /* LVDS state */ 630 /* LVDS state */
631 if (IS_I965G(dev) && !IS_IGDNG(dev)) 631 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
632 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 632 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
633 633
634 if (IS_IGDNG(dev)) { 634 if (IS_IRONLAKE(dev)) {
635 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 635 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
636 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 636 } else if (IS_MOBILE(dev) && !IS_I830(dev))
637 I915_WRITE(LVDS, dev_priv->saveLVDS); 637 I915_WRITE(LVDS, dev_priv->saveLVDS);
638 638
639 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev)) 639 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev))
640 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 640 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
641 641
642 if (IS_IGDNG(dev)) { 642 if (IS_IRONLAKE(dev)) {
643 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 643 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
644 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 644 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
645 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 645 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
@@ -679,7 +679,7 @@ void i915_restore_display(struct drm_device *dev)
679 } 679 }
680 680
681 /* VGA state */ 681 /* VGA state */
682 if (IS_IGDNG(dev)) 682 if (IS_IRONLAKE(dev))
683 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 683 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
684 else 684 else
685 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 685 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
@@ -710,7 +710,7 @@ int i915_save_state(struct drm_device *dev)
710 i915_save_display(dev); 710 i915_save_display(dev);
711 711
712 /* Interrupt state */ 712 /* Interrupt state */
713 if (IS_IGDNG(dev)) { 713 if (IS_IRONLAKE(dev)) {
714 dev_priv->saveDEIER = I915_READ(DEIER); 714 dev_priv->saveDEIER = I915_READ(DEIER);
715 dev_priv->saveDEIMR = I915_READ(DEIMR); 715 dev_priv->saveDEIMR = I915_READ(DEIMR);
716 dev_priv->saveGTIER = I915_READ(GTIER); 716 dev_priv->saveGTIER = I915_READ(GTIER);
@@ -787,7 +787,7 @@ int i915_restore_state(struct drm_device *dev)
787 i915_restore_display(dev); 787 i915_restore_display(dev);
788 788
789 /* Interrupt state */ 789 /* Interrupt state */
790 if (IS_IGDNG(dev)) { 790 if (IS_IRONLAKE(dev)) {
791 I915_WRITE(DEIER, dev_priv->saveDEIER); 791 I915_WRITE(DEIER, dev_priv->saveDEIER);
792 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 792 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
793 I915_WRITE(GTIER, dev_priv->saveGTIER); 793 I915_WRITE(GTIER, dev_priv->saveGTIER);