drm/i915: clear up backlight #define confusion on gen4+

- Regroup definitions for BLC_PWM_CTL so that they're all together and
  and ordered according to the bitfields.

- Add all missing definitions for BLC_PWM_CTL2.

- Use the BLM_ (for backlight modulation) prefix consistently.

- Note that combination mode (i.e. also taking the legacy backlight
  control value from pci config space into account) is gen4 only.

- Move the new registers for PCH-split machines up, they're an almost
  match for the gen4 defitions.  Prefix the special PCH-only bits with
  BLM_PCH_. Also add the pipe C select bit for ivb.

- Rip out the second pair of PCH polarity definitions - they're only
  valid on early (pre-production) ilk silicon.

- Adapt the existing code to use the new definitions. This has the
  nice benefit of killing a magic (1 << 30) left behind be Jesse
  Barnes.

No functional changes in this patch.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 35 insertions, 20 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 20244b971fc6..c4b1a2b45bb4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1807,18 +1807,35 @@
 #define PFIT_AUTO_RATIOS 0x61238
 
 /* Backlight control */
-#define BLC_PWM_CTL             0x61254
-#define   BACKLIGHT_MODULATION_FREQ_SHIFT               (17)
 #define BLC_PWM_CTL2            0x61250 /* 965+ only */
-#define   BLM_COMBINATION_MODE (1 << 30)
+#define   BLM_PWM_ENABLE                (1 << 31)
+#define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
+#define   BLM_PIPE_SELECT               (1 << 29)
+#define   BLM_PIPE_SELECT_IVB           (3 << 29)
+#define   BLM_PIPE_A                    (0 << 29)
+#define   BLM_PIPE_B                    (1 << 29)
+#define   BLM_PIPE_C                    (2 << 29) /* ivb + */
+#define   BLM_PIPE(pipe)                ((pipe) << 29)
+#define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
+#define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
+#define   BLM_PHASE_IN_ENABLE           (1 << 25)
+#define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
+#define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
+#define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
+#define   BLM_PHASE_IN_COUNT_SHIFT      (8)
+#define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
+#define   BLM_PHASE_IN_INCR_SHIFT       (0)
+#define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
+#define BLC_PWM_CTL             0x61254
 /*
  * This is the most significant 15 bits of the number of backlight cycles in a
  * complete cycle of the modulated backlight control.
  *
  * The actual value is this field multiplied by two.
  */
-#define   BACKLIGHT_MODULATION_FREQ_MASK                (0x7fff << 17)
-#define   BLM_LEGACY_MODE                               (1 << 16)
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
+#define   BACKLIGHT_MODULATION_FREQ_MASK        (0x7fff << 17)
+#define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
 /*
  * This is the number of cycles out of the backlight modulation cycle for which
  * the backlight is on.
@@ -1833,6 +1850,19 @@
 
 #define BLC_HIST_CTL            0x61260
 
+/* New registers for PCH-split platforms. Safe where new bits show up, the
+ * register layout machtes with gen4 BLC_PWM_CTL[12]. */
+#define BLC_PWM_CPU_CTL2        0x48250
+#define BLC_PWM_CPU_CTL         0x48254
+
+/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
+#define BLC_PWM_PCH_CTL1        0xc8250
+#define   BLM_PCH_PWM_ENABLE                    (1 << 30)
+#define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
+#define   BLM_PCH_POLARITY                      (1 << 29)
+#define BLC_PWM_PCH_CTL2        0xc8254
+
 /* TV port control */
 #define TV_CTL                  0x68000
 /** Enables the TV encoder */
@@ -3840,21 +3870,6 @@
 #define PCH_LVDS        0xe1180
 #define  LVDS_DETECTED  (1 << 1)
 
-#define BLC_PWM_CPU_CTL2        0x48250
-#define  PWM_ENABLE             (1 << 31)
-#define  PWM_PIPE_A             (0 << 29)
-#define  PWM_PIPE_B             (1 << 29)
-#define BLC_PWM_CPU_CTL         0x48254
-
-#define BLC_PWM_PCH_CTL1        0xc8250
-#define  PWM_PCH_ENABLE         (1 << 31)
-#define  PWM_POLARITY_ACTIVE_LOW        (1 << 29)
-#define  PWM_POLARITY_ACTIVE_HIGH       (0 << 29)
-#define  PWM_POLARITY_ACTIVE_LOW2       (1 << 28)
-#define  PWM_POLARITY_ACTIVE_HIGH2      (0 << 28)
-
-#define BLC_PWM_PCH_CTL2        0xc8254
-
 #define PCH_PP_STATUS           0xc7200
 #define PCH_PP_CONTROL          0xc7204
 #define  PANEL_UNLOCK_REGS      (0xabcd << 16)