drm/i915: framebuffer compression for GM45+

Add support for framebuffer compression on GM45 and above.  Removes
some unnecessary I915_HAS_FBC checks as well (this is now part of the
FBC display function).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 27 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f3d41397ce74..8122a72828e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -351,6 +351,33 @@
 
 #define FBC_LL_SIZE             (1536)
 
+/* Framebuffer compression for GM45+ */
+#define DPFC_CB_BASE            0x3200
+#define DPFC_CONTROL            0x3208
+#define   DPFC_CTL_EN           (1<<31)
+#define   DPFC_CTL_PLANEA       (0<<30)
+#define   DPFC_CTL_PLANEB       (1<<30)
+#define   DPFC_CTL_FENCE_EN     (1<<29)
+#define   DPFC_SR_EN            (1<<10)
+#define   DPFC_CTL_LIMIT_1X     (0<<6)
+#define   DPFC_CTL_LIMIT_2X     (1<<6)
+#define   DPFC_CTL_LIMIT_4X     (2<<6)
+#define DPFC_RECOMP_CTL         0x320c
+#define   DPFC_RECOMP_STALL_EN  (1<<27)
+#define   DPFC_RECOMP_STALL_WM_SHIFT (16)
+#define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
+#define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
+#define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
+#define DPFC_STATUS             0x3210
+#define   DPFC_INVAL_SEG_SHIFT  (16)
+#define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
+#define   DPFC_COMP_SEG_SHIFT   (0)
+#define   DPFC_COMP_SEG_MASK    (0x000003ff)
+#define DPFC_STATUS2            0x3214
+#define DPFC_FENCE_YOFF         0x3218
+#define DPFC_CHICKEN            0x3224
+#define   DPFC_HT_MODIFY        (1<<31)
+
 /*
  * GPIO regs
  */