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authorZhao Yakui <yakui.zhao@intel.com>2010-06-12 02:32:25 -0400
committerEric Anholt <eric@anholt.net>2010-08-01 22:03:43 -0400
commit4fe5e61180d8ea2268d6e64972d90efbe2bab4aa (patch)
tree872f4cdcb027fb6144032dcde67e176c8b99be14 /drivers/gpu/drm/i915/i915_reg.h
parent1b07e04e9cd443fc333f4036d129ba7c08d340c4 (diff)
drm/i915: Apply self-refresh watermark calculation for cursor plane
In SR mode cursor plane watermark calculation uses same formula like display plane. This one fixes the case for 965G and G45. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b637fbf592ec..1f741a6d0b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2160,6 +2160,9 @@
2160#define PINEVIEW_CURSOR_DFT_WM 0 2160#define PINEVIEW_CURSOR_DFT_WM 0
2161#define PINEVIEW_CURSOR_GUARD_WM 5 2161#define PINEVIEW_CURSOR_GUARD_WM 5
2162 2162
2163#define I965_CURSOR_FIFO 64
2164#define I965_CURSOR_MAX_WM 32
2165#define I965_CURSOR_DFT_WM 8
2163 2166
2164/* define the Watermark register on Ironlake */ 2167/* define the Watermark register on Ironlake */
2165#define WM0_PIPEA_ILK 0x45100 2168#define WM0_PIPEA_ILK 0x45100