drm: Add GEM ("graphics execution manager") to i915 driver.

GEM allows the creation of persistent buffer objects accessible by the
graphics device through new ioctls for managing execution of commands on the
device.  The userland API is almost entirely driver-specific to ensure that
any driver building on this model can easily map the interface to individual
driver requirements.

GEM is used by the 2d driver for managing its internal state allocations and
will be used for pixmap storage to reduce memory consumption and enable
zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable
GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 24 insertions, 13 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43ad2cb8b9f5..5c2d9f206d05 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,19 +25,6 @@
 #ifndef _I915_REG_H_
 #define _I915_REG_H_
 
-/* MCH MMIO space */
-/** 915-945 and GM965 MCH register controlling DRAM channel access */
-#define DCC             0x200
-#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
-#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
-#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
-#define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
-#define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
-
-/** 965 MCH register controlling DRAM channel configuration */
-#define CHDECMISC               0x111
-#define CHDECMISC_FLEXMEMORY            (1 << 1)
-
 /*
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.
@@ -516,6 +503,30 @@
 #define PALETTE_A               0x0a000
 #define PALETTE_B               0x0a800
 
+/* MCH MMIO space */
+
+/*
+ * MCHBAR mirror.
+ *
+ * This mirrors the MCHBAR MMIO space whose location is determined by
+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
+ * every way.  It is not accessible from the CP register read instructions.
+ *
+ */
+#define MCHBAR_MIRROR_BASE      0x10000
+
+/** 915-945 and GM965 MCH register controlling DRAM channel access */
+#define DCC                     0x10200
+#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
+#define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
+#define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
+
+/** 965 MCH register controlling DRAM channel configuration */
+#define C0DRB3                  0x10206
+#define C1DRB3                  0x10606
+
 /*
  * Overlay regs
  */