drm/i915/skl: Tune IZ hashing when subslices are unbalanced

When one EU is disabled in a particular subslice, we can tune how the
work is spread between subslices to improve EU utilization.

v2: - Use a bitfield to record which subslice(s) has(have) 7 EUs. That
      will also make the machinery work if several sublices have 7 EUs.
      (Jeff Mcgee)
    - Only apply the different hashing algorithm if the slice is
      effectively unbalanced by checking there's a single subslice with
      7 EUs. (Jeff Mcgee)

v3: Fix typo in comment (Jeff Mcgee)

Issue: VIZ-3845
Cc: Jeff Mcgee <jeff.mcgee@intel.com>
Reviewed-by: Jeff Mcgee <jeff.mcgee@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5fab90c84c5d..c2124119692d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1351,6 +1351,8 @@ enum skl_disp_power_wells {
 #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
 #define   GEN6_WIZ_HASHING_MASK                         GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
+#define   GEN9_IZ_HASHING_MASK(slice)                   (0x3 << (slice * 2))
+#define   GEN9_IZ_HASHING(slice, val)                   ((val) << (slice * 2))
 
 #define GFX_MODE        0x02520
 #define GFX_MODE_GEN7   0x0229c