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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2015-04-21 12:49:11 -0400
committerJani Nikula <jani.nikula@intel.com>2015-04-23 16:48:18 -0400
commit9535c4757b881e06fae72a857485ad57c422b8d2 (patch)
tree6362a8d89171fba94539c0475d6b2ccb2ea9e7f2 /drivers/gpu/drm/i915/i915_reg.h
parent37ef01ab5d24d1d520dc79f6a98099d451c2a901 (diff)
drm/i915: cope with large i2c transfers
The hardware, according to the specs, is limited to 256 byte transfers, and current driver has no protections in case users attempt to do larger transfers. The code will just stomp over status register and mayhem ensues. Let's split larger transfers into digestable chunks. Doing this allows Atmel MXT driver on Pixel 1 function properly (it hasn't since commit 9d8dc3e529a19e427fd379118acd132520935c5d "Input: atmel_mxt_ts - implement T44 message handling" which tries to consume multiple touchscreen/touchpad reports in a single transaction). Cc: stable@vger.kernel.org Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6e59a4..3da1af46625c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1807,6 +1807,7 @@ enum skl_disp_power_wells {
1807#define GMBUS_CYCLE_INDEX (2<<25) 1807#define GMBUS_CYCLE_INDEX (2<<25)
1808#define GMBUS_CYCLE_STOP (4<<25) 1808#define GMBUS_CYCLE_STOP (4<<25)
1809#define GMBUS_BYTE_COUNT_SHIFT 16 1809#define GMBUS_BYTE_COUNT_SHIFT 16
1810#define GMBUS_BYTE_COUNT_MAX 256U
1810#define GMBUS_SLAVE_INDEX_SHIFT 8 1811#define GMBUS_SLAVE_INDEX_SHIFT 8
1811#define GMBUS_SLAVE_ADDR_SHIFT 1 1812#define GMBUS_SLAVE_ADDR_SHIFT 1
1812#define GMBUS_SLAVE_READ (1<<0) 1813#define GMBUS_SLAVE_READ (1<<0)