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authorDamien Lespiau <damien.lespiau@intel.com>2015-02-09 14:33:17 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-13 17:28:34 -0500
commit9370cd987e91d6d652ebe6d883fbc51b10df2403 (patch)
treed72793e42e3d9ce9140d5a302f96045fa7a6c143 /drivers/gpu/drm/i915/i915_reg.h
parent8d2054941071d10c8bbe120dd2160be8ae21f267 (diff)
drm/i915/skl: Implement WaDisablePartialResolveInVc
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b00d323095af..b610764768d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1483,6 +1483,7 @@ enum skl_disp_power_wells {
1483#define CACHE_MODE_1 0x7004 /* IVB+ */ 1483#define CACHE_MODE_1 0x7004 /* IVB+ */
1484#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1484#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1485#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1485#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1486#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
1486 1487
1487#define GEN6_BLITTER_ECOSKPD 0x221d0 1488#define GEN6_BLITTER_ECOSKPD 0x221d0
1488#define GEN6_BLITTER_LOCK_SHIFT 16 1489#define GEN6_BLITTER_LOCK_SHIFT 16