drm/i915/skl: Add SKL HW status to SSEU status

Add a new section to the 'i915_sseu_status' debugfs entry to
report the currently enabled counts of slice, subslice, and
execution units on the device. The count of enabled subslice
per slice represents the most enabled subslice on any one
slice for devices where imbalances may exist. Similarly, the
count of enabled EU per subslice represents the most enabled
EU on any one subslice.

Collect this device status for Skylake by reading the Gen9
power gate control ack message registers. Power gate control
operates on EU in pairs, therefore our reported counts of
enabled EU can be overestimated by one for each pair in which
one EU is fused-off.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 20 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9d4367ee8d4..4da883b2c3c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6209,6 +6209,26 @@ enum skl_disp_power_wells {
 #define   GEN6_RC6                      3
 #define   GEN6_RC7                      4
 
+#define GEN9_SLICE0_PGCTL_ACK           0x804c
+#define GEN9_SLICE1_PGCTL_ACK           0x8050
+#define GEN9_SLICE2_PGCTL_ACK           0x8054
+#define   GEN9_PGCTL_SLICE_ACK          (1 << 0)
+
+#define GEN9_SLICE0_SS01_EU_PGCTL_ACK   0x805c
+#define GEN9_SLICE0_SS23_EU_PGCTL_ACK   0x8060
+#define GEN9_SLICE1_SS01_EU_PGCTL_ACK   0x8064
+#define GEN9_SLICE1_SS23_EU_PGCTL_ACK   0x8068
+#define GEN9_SLICE2_SS01_EU_PGCTL_ACK   0x806c
+#define GEN9_SLICE2_SS23_EU_PGCTL_ACK   0x8070
+#define   GEN9_PGCTL_SSA_EU08_ACK       (1 << 0)
+#define   GEN9_PGCTL_SSA_EU19_ACK       (1 << 2)
+#define   GEN9_PGCTL_SSA_EU210_ACK      (1 << 4)
+#define   GEN9_PGCTL_SSA_EU311_ACK      (1 << 6)
+#define   GEN9_PGCTL_SSB_EU08_ACK       (1 << 8)
+#define   GEN9_PGCTL_SSB_EU19_ACK       (1 << 10)
+#define   GEN9_PGCTL_SSB_EU210_ACK      (1 << 12)
+#define   GEN9_PGCTL_SSB_EU311_ACK      (1 << 14)
+
 #define GEN7_MISCCPCTL                  (0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE    (1<<0)