drm/i915: New offset for reading frequencies on CHV.

Use new Sideband offset to read max/min/gaur freq based on the SKU it
is running on. Based on the Number of EU, we read different bits to
identify the max frequencies at which system can run.

v2: reuse mask definitions & INTEL_INFO() to get device info (Ville)

v3: add break in switch conditions (Ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d9692f947d8f..2dcb1b342cb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -605,6 +605,15 @@ enum punit_power_well {
 #define PUNIT_FUSE_BUS2                         0xf6 /* bits 47:40 */
 #define PUNIT_FUSE_BUS1                         0xf5 /* bits 55:48 */
 
+#define FB_GFX_FMAX_AT_VMAX_FUSE                0x136
+#define FB_GFX_FREQ_FUSE_MASK                   0xff
+#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT   24
+#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT   16
+#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT   8
+
+#define FB_GFX_FMIN_AT_VMIN_FUSE                0x137
+#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT          8
+
 #define PUNIT_GPU_STATUS_REG                    0xdb
 #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
 #define PUNIT_GPU_STATUS_MAX_FREQ_MASK          0xff