drm/i915: add ValleyView clock gating init

Set required clock gating and chicken bits on VLV.

v2: set PIXEL_SUBSPAN_COLLECT_OPT_DISABLE too (Ben)
    move function below ivb version to pretend to be consistent (Ben)

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 18 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65f5849f2ad6..58914b4f5357 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -633,6 +633,9 @@
 #define   ECO_GATING_CX_ONLY    (1<<3)
 #define   ECO_FLIP_DONE         (1<<0)
 
+#define CACHE_MODE_1            0x7004 /* IVB+ */
+#define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
+
 /* GEN6 interrupt control */
 #define GEN6_RENDER_HWSTAM      0x2098
 #define GEN6_RENDER_IMR         0x20a8
@@ -3184,6 +3187,20 @@
 #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
 #define  DISP_FBC_WM_DIS                (1<<15)
 
+/* GEN7 chicken */
+#define GEN7_COMMON_SLICE_CHICKEN1              0x7010
+# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
+
+#define GEN7_L3CNTLREG1                         0xB01C
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER           0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE                                0x20000000
+
+/* WaCatErrorRejectionIssue */
+#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          0x9030
+#define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB       (1<<11)
+
 /* PCH */
 
 /* south display engine interrupt */
@@ -3787,6 +3804,7 @@
 #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
 
 #define GEN6_UCGCTL2                            0x9404
+# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE                (1 << 13)
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
 # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)