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authorEugeni Dodonov <eugeni.dodonov@intel.com>2012-03-29 11:32:23 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-04-09 12:03:59 -0400
commite7e104c3785a5a88ce9a58f0bfd0722e53217f47 (patch)
treeb4899c9c4088cfaf35262f0a2815d78efc8b27bc /drivers/gpu/drm/i915/i915_reg.h
parent2b139522008b824ba17d5160085ce70f940839a0 (diff)
drm/i915: add DDI registers
There is one set of such registers for each pipe (A/B/C/EDP). v2: update to use DDI PORTS enum v1 Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bca37b3082c5..61eca8b9679f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4036,4 +4036,30 @@
4036#define HSW_PWR_WELL_FORCE_ON (1<<19) 4036#define HSW_PWR_WELL_FORCE_ON (1<<19)
4037#define HSW_PWR_WELL_CTL6 0x45414 4037#define HSW_PWR_WELL_CTL6 0x45414
4038 4038
4039/* Per-pipe DDI Function Control */
4040#define PIPE_DDI_FUNC_CTL_A 0x60400
4041#define PIPE_DDI_FUNC_CTL_B 0x61400
4042#define PIPE_DDI_FUNC_CTL_C 0x62400
4043#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
4044#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
4045 PIPE_DDI_FUNC_CTL_A, \
4046 PIPE_DDI_FUNC_CTL_B)
4047#define PIPE_DDI_FUNC_ENABLE (1<<31)
4048/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
4049#define PIPE_DDI_PORT_MASK (0xf<<28)
4050#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
4051#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
4052#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
4053#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
4054#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
4055#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
4056#define PIPE_DDI_BPC_8 (0<<20)
4057#define PIPE_DDI_BPC_10 (1<<20)
4058#define PIPE_DDI_BPC_6 (2<<20)
4059#define PIPE_DDI_BPC_12 (3<<20)
4060#define PIPE_DDI_BFI_ENABLE (1<<4)
4061#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
4062#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
4063#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
4064
4039#endif /* _I915_REG_H_ */ 4065#endif /* _I915_REG_H_ */