drm/i915: gen7: Implement an L3 caching workaround.

This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80fd6b5d4287..ca4737e5cdfd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3028,6 +3028,13 @@
 #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
 #define  DISP_FBC_WM_DIS                (1<<15)
 
+/* GEN7 chicken */
+#define GEN7_L3CNTLREG1                         0xB01C
+#define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C4FFF8C
+
+#define GEN7_L3_CHICKEN_MODE_REGISTER           0xB030
+#define  GEN7_WA_L3_CHICKEN_MODE                                0x20000000
+
 /* PCH */
 
 /* south display engine interrupt */