diff options
| author | Eric Anholt <eric@anholt.net> | 2010-03-18 16:21:14 -0400 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-03-18 19:48:01 -0400 |
| commit | 8956c8bba5b11b3d3aec000e6c6184943011a8d4 (patch) | |
| tree | e3e712d6c58108b8937827f5c3cdecc3ae8f5afc /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 66f6ff09ff67c45919b336395c4d7d0ed3a97edc (diff) | |
drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2720bc2cd678..cbbf59f56dfa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -2176,6 +2176,14 @@ | |||
| 2176 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | 2176 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
| 2177 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | 2177 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
| 2178 | 2178 | ||
| 2179 | #define PCH_DSPCLK_GATE_D 0x42020 | ||
| 2180 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) | ||
| 2181 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) | ||
| 2182 | |||
| 2183 | #define PCH_3DCGDIS0 0x46020 | ||
| 2184 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | ||
| 2185 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | ||
| 2186 | |||
| 2179 | #define FDI_PLL_FREQ_CTL 0x46030 | 2187 | #define FDI_PLL_FREQ_CTL 0x46030 |
| 2180 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) | 2188 | #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) |
| 2181 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 | 2189 | #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |