diff options
author | Xiang, Haihao <haihao.xiang@intel.com> | 2010-09-19 09:40:43 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-21 06:19:57 -0400 |
commit | 881f47b64723f4d697084533491a489e3e74b10f (patch) | |
tree | 8659b98e6dc7706af79e2d8c6894bc9dd2cb6217 /drivers/gpu/drm/i915/i915_reg.h | |
parent | a3f07cd53e31c1c27364e56266a541b9467c1895 (diff) |
drm/i915: add a new BSD ring buffer for Sandybridge
This ring buffer is used for video decoding/encoding on Sandybridge.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b46e580421e1..8d51de0e01f2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -197,11 +197,11 @@ | |||
197 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | 197 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
198 | #define MI_STORE_DWORD_INDEX_SHIFT 2 | 198 | #define MI_STORE_DWORD_INDEX_SHIFT 2 |
199 | #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) | 199 | #define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1) |
200 | #define MI_FLUSH_DW MI_INSTR(0x26, 2) /* for GEN6 */ | ||
200 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) | 201 | #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) |
201 | #define MI_BATCH_NON_SECURE (1) | 202 | #define MI_BATCH_NON_SECURE (1) |
202 | #define MI_BATCH_NON_SECURE_I965 (1<<8) | 203 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
203 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) | 204 | #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) |
204 | |||
205 | /* | 205 | /* |
206 | * 3D instructions used by the kernel | 206 | * 3D instructions used by the kernel |
207 | */ | 207 | */ |
@@ -484,6 +484,28 @@ | |||
484 | #define BSD_HWS_PGA 0x04080 | 484 | #define BSD_HWS_PGA 0x04080 |
485 | 485 | ||
486 | /* | 486 | /* |
487 | * video command stream instruction and interrupt control register defines | ||
488 | * for GEN6 | ||
489 | */ | ||
490 | #define GEN6_BSD_RING_TAIL 0x12030 | ||
491 | #define GEN6_BSD_RING_HEAD 0x12034 | ||
492 | #define GEN6_BSD_RING_START 0x12038 | ||
493 | #define GEN6_BSD_RING_CTL 0x1203c | ||
494 | #define GEN6_BSD_RING_ACTHD 0x12074 | ||
495 | #define GEN6_BSD_HWS_PGA 0x14080 | ||
496 | |||
497 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 | ||
498 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) | ||
499 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) | ||
500 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 | ||
501 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) | ||
502 | |||
503 | #define GEN6_BSD_IMR 0x120a8 | ||
504 | #define GEN6_BSD_IMR_USER_INTERRUPT (1 << 12) | ||
505 | |||
506 | #define GEN6_BSD_RNCID 0x12198 | ||
507 | |||
508 | /* | ||
487 | * Framebuffer compression (915+ only) | 509 | * Framebuffer compression (915+ only) |
488 | */ | 510 | */ |
489 | 511 | ||
@@ -2598,7 +2620,7 @@ | |||
2598 | #define GT_SYNC_STATUS (1 << 2) | 2620 | #define GT_SYNC_STATUS (1 << 2) |
2599 | #define GT_USER_INTERRUPT (1 << 0) | 2621 | #define GT_USER_INTERRUPT (1 << 0) |
2600 | #define GT_BSD_USER_INTERRUPT (1 << 5) | 2622 | #define GT_BSD_USER_INTERRUPT (1 << 5) |
2601 | 2623 | #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) | |
2602 | 2624 | ||
2603 | #define GTISR 0x44010 | 2625 | #define GTISR 0x44010 |
2604 | #define GTIMR 0x44014 | 2626 | #define GTIMR 0x44014 |