aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_irq.c
diff options
context:
space:
mode:
authorChris Wilson <chris@chris-wilson.co.uk>2012-04-24 17:59:46 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-05-03 05:18:17 -0400
commit2c8ba29f15b57b0a587fae2a83ce906c82031d18 (patch)
treeb63b7c17eff13733a0cd45de008c8311a6a3179b /drivers/gpu/drm/i915/i915_irq.c
parent4f7d1e79b1967d2f1a718d4b9afbb23053858c0a (diff)
drm/i915: Remove gen3 irq code from gen4 irq routine
And a couple of miscellaneous cleanups to the main body of the IRQ loop; move per-loop condition variables within the scope of the loop and move the old DRI1 breadcrumb to the tail of the function and so only execute it once. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c27
1 files changed, 10 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7ea95b64891f..874d62b78fbe 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2683,23 +2683,17 @@ static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2683 struct drm_i915_master_private *master_priv; 2683 struct drm_i915_master_private *master_priv;
2684 u32 iir, new_iir; 2684 u32 iir, new_iir;
2685 u32 pipe_stats[I915_MAX_PIPES]; 2685 u32 pipe_stats[I915_MAX_PIPES];
2686 u32 vblank_status;
2687 int vblank = 0;
2688 unsigned long irqflags; 2686 unsigned long irqflags;
2689 int irq_received; 2687 int irq_received;
2690 int ret = IRQ_NONE, pipe; 2688 int ret = IRQ_NONE, pipe;
2691 bool blc_event = false;
2692 2689
2693 atomic_inc(&dev_priv->irq_received); 2690 atomic_inc(&dev_priv->irq_received);
2694 2691
2695 iir = I915_READ(IIR); 2692 iir = I915_READ(IIR);
2696 2693
2697 if (INTEL_INFO(dev)->gen >= 4)
2698 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
2699 else
2700 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
2701
2702 for (;;) { 2694 for (;;) {
2695 bool blc_event = false;
2696
2703 irq_received = iir != 0; 2697 irq_received = iir != 0;
2704 2698
2705 /* Can't rely on pipestat interrupt bit in iir as it might 2699 /* Can't rely on pipestat interrupt bit in iir as it might
@@ -2751,13 +2745,6 @@ static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2751 I915_WRITE(IIR, iir); 2745 I915_WRITE(IIR, iir);
2752 new_iir = I915_READ(IIR); /* Flush posted writes */ 2746 new_iir = I915_READ(IIR); /* Flush posted writes */
2753 2747
2754 if (dev->primary->master) {
2755 master_priv = dev->primary->master->driver_priv;
2756 if (master_priv->sarea_priv)
2757 master_priv->sarea_priv->last_dispatch =
2758 READ_BREADCRUMB(dev_priv);
2759 }
2760
2761 if (iir & I915_USER_INTERRUPT) 2748 if (iir & I915_USER_INTERRUPT)
2762 notify_ring(dev, &dev_priv->ring[RCS]); 2749 notify_ring(dev, &dev_priv->ring[RCS]);
2763 if (iir & I915_BSD_USER_INTERRUPT) 2750 if (iir & I915_BSD_USER_INTERRUPT)
@@ -2770,9 +2757,8 @@ static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2770 intel_prepare_page_flip(dev, 1); 2757 intel_prepare_page_flip(dev, 1);
2771 2758
2772 for_each_pipe(pipe) { 2759 for_each_pipe(pipe) {
2773 if (pipe_stats[pipe] & vblank_status && 2760 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2774 drm_handle_vblank(dev, pipe)) { 2761 drm_handle_vblank(dev, pipe)) {
2775 vblank++;
2776 i915_pageflip_stall_check(dev, pipe); 2762 i915_pageflip_stall_check(dev, pipe);
2777 intel_finish_page_flip(dev, pipe); 2763 intel_finish_page_flip(dev, pipe);
2778 } 2764 }
@@ -2803,6 +2789,13 @@ static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2803 iir = new_iir; 2789 iir = new_iir;
2804 } 2790 }
2805 2791
2792 if (dev->primary->master) {
2793 master_priv = dev->primary->master->driver_priv;
2794 if (master_priv->sarea_priv)
2795 master_priv->sarea_priv->last_dispatch =
2796 READ_BREADCRUMB(dev_priv);
2797 }
2798
2806 return ret; 2799 return ret;
2807} 2800}
2808 2801