aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_irq.c
diff options
context:
space:
mode:
authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-04-09 06:28:50 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-20 09:30:07 -0400
commit8e5fd599eb219f1054e39b40d18b217af669eea9 (patch)
treec1ebd1855cdf6fcbbd69630cd5e4840d83f87927 /drivers/gpu/drm/i915/i915_irq.c
parent3278f67fa7c99d6739304ffe3c04fadd6d74ff80 (diff)
drm/i915/chv: Make CHV irq handler loop until all interrupts are consumed
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c29
1 files changed, 14 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4811908ee551..787ad93c5fa5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1787,30 +1787,29 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1787 u32 master_ctl, iir; 1787 u32 master_ctl, iir;
1788 irqreturn_t ret = IRQ_NONE; 1788 irqreturn_t ret = IRQ_NONE;
1789 1789
1790 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; 1790 for (;;) {
1791 iir = I915_READ(VLV_IIR); 1791 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1792 iir = I915_READ(VLV_IIR);
1792 1793
1793 if (master_ctl == 0 && iir == 0) 1794 if (master_ctl == 0 && iir == 0)
1794 return IRQ_NONE; 1795 break;
1795 1796
1796 I915_WRITE(GEN8_MASTER_IRQ, 0); 1797 I915_WRITE(GEN8_MASTER_IRQ, 0);
1797 1798
1798 gen8_gt_irq_handler(dev, dev_priv, master_ctl); 1799 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1799 1800
1800 valleyview_pipestat_irq_handler(dev, iir); 1801 valleyview_pipestat_irq_handler(dev, iir);
1801 1802
1802 /* Consume port. Then clear IIR or we'll miss events */ 1803 /* Consume port. Then clear IIR or we'll miss events */
1803 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1804 i9xx_hpd_irq_handler(dev); 1804 i9xx_hpd_irq_handler(dev);
1805 ret = IRQ_HANDLED;
1806 }
1807 1805
1808 I915_WRITE(VLV_IIR, iir); 1806 I915_WRITE(VLV_IIR, iir);
1809 1807
1810 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); 1808 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1811 POSTING_READ(GEN8_MASTER_IRQ); 1809 POSTING_READ(GEN8_MASTER_IRQ);
1812 1810
1813 ret = IRQ_HANDLED; 1811 ret = IRQ_HANDLED;
1812 }
1814 1813
1815 return ret; 1814 return ret;
1816} 1815}