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authorChris Wilson <chris@chris-wilson.co.uk>2015-03-18 05:48:23 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-20 06:48:14 -0400
commit6f4b12f89c78fd0030aa51ead17eaf234108f60d (patch)
treecde9fd2950f08a7a9c164923797be738cb7ef1d0 /drivers/gpu/drm/i915/i915_irq.c
parent43cf3bf084ba097463d67e756ff821505bdaa69d (diff)
drm/i915: Use down ei for manual Baytrail RPS calculations
Use both up/down manual ei calcuations for symmetry and greater flexibility for reclocking, instead of faking the down interrupt based on a fixed integer number of up interrupts. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c15
1 files changed, 2 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8d8d33d068dd..6d8340d5a111 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1033,7 +1033,6 @@ void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1033{ 1033{
1034 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); 1034 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1035 dev_priv->rps.up_ei = dev_priv->rps.down_ei; 1035 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1036 dev_priv->rps.ei_interrupt_count = 0;
1037} 1036}
1038 1037
1039static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) 1038static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
@@ -1041,23 +1040,13 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1041 struct intel_rps_ei now; 1040 struct intel_rps_ei now;
1042 u32 events = 0; 1041 u32 events = 0;
1043 1042
1044 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0) 1043 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1045 return 0; 1044 return 0;
1046 1045
1047 vlv_c0_read(dev_priv, &now); 1046 vlv_c0_read(dev_priv, &now);
1048 if (now.cz_clock == 0) 1047 if (now.cz_clock == 0)
1049 return 0; 1048 return 0;
1050 1049
1051 /*
1052 * To down throttle, C0 residency should be less than down threshold
1053 * for continous EI intervals. So calculate down EI counters
1054 * once in VLV_INT_COUNT_FOR_DOWN_EI
1055 */
1056 if (++dev_priv->rps.ei_interrupt_count >= VLV_INT_COUNT_FOR_DOWN_EI) {
1057 pm_iir |= GEN6_PM_RP_DOWN_EI_EXPIRED;
1058 dev_priv->rps.ei_interrupt_count = 0;
1059 }
1060
1061 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { 1050 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1062 if (!vlv_c0_above(dev_priv, 1051 if (!vlv_c0_above(dev_priv,
1063 &dev_priv->rps.down_ei, &now, 1052 &dev_priv->rps.down_ei, &now,
@@ -4254,7 +4243,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4254 /* Let's track the enabled rps events */ 4243 /* Let's track the enabled rps events */
4255 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 4244 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
4256 /* WaGsvRC0ResidencyMethod:vlv */ 4245 /* WaGsvRC0ResidencyMethod:vlv */
4257 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED; 4246 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4258 else 4247 else
4259 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; 4248 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4260 4249