drm/i915: create macros to handle masked bits

... and put them to so good use.

Note that there's functional change in vlv clock gating code, we now
no longer spuriously read back the current value of the bit. According
to Bspec the high bits should always read zero, so ORing this in
should have no effect.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d45b43a35f15..26172eef9787 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1648,7 +1648,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
 
         /* maintain vblank delivery even in deep C-states */
         if (dev_priv->info->gen == 3)
-                I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
+                I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
         return 0;
@@ -1722,8 +1722,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
 
         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
         if (dev_priv->info->gen == 3)
-                I915_WRITE(INSTPM,
-                           INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
+                I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
 
         i915_disable_pipestat(dev_priv, pipe,
                               PIPE_VBLANK_INTERRUPT_ENABLE |