drm/i915: add dev_priv->pm_irq_mask

Just like irq_mask and gt_irq_mask, use it to track the status of
GEN6_PMIMR so we don't need to read it again every time we call
snb_update_pm_irq.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 5 deletions

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index efe3fc671e1e..8872e1955c45 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -142,16 +142,17 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
                               uint32_t interrupt_mask,
                               uint32_t enabled_irq_mask)
 {
-        uint32_t pmimr, new_val;
+        uint32_t new_val;
 
         assert_spin_locked(&dev_priv->irq_lock);
 
-        pmimr = new_val = I915_READ(GEN6_PMIMR);
+        new_val = dev_priv->pm_irq_mask;
         new_val &= ~interrupt_mask;
         new_val |= (~enabled_irq_mask & interrupt_mask);
 
-        if (new_val != pmimr) {
-                I915_WRITE(GEN6_PMIMR, new_val);
+        if (new_val != dev_priv->pm_irq_mask) {
+                dev_priv->pm_irq_mask = new_val;
+                I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
                 POSTING_READ(GEN6_PMIMR);
         }
 }
@@ -2217,8 +2218,9 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
                 if (HAS_VEBOX(dev))
                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
 
+                dev_priv->pm_irq_mask = 0xffffffff;
                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
-                I915_WRITE(GEN6_PMIMR, 0xffffffff);
+                I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
                 I915_WRITE(GEN6_PMIER, pm_irqs);
                 POSTING_READ(GEN6_PMIER);
         }