diff options
author | Li Peng <peng.li@linux.intel.com> | 2010-01-22 11:12:58 -0500 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-01-25 12:14:30 -0500 |
commit | c062df61966405b0be6743bfb0cf300dca2fa7c2 (patch) | |
tree | ae4a82215c6f0ae82021b3d45427e69de16ff1a5 /drivers/gpu/drm/i915/i915_irq.c | |
parent | 0ce907f89118aa8748f950700b6919b1d8d8a038 (diff) |
drm/i915: enable vblank interrupt on ironlake
so far vblank interrupt on ironlake is disabled, this would cause
bad gfx performance if userspace calls drm_wait_vblank. This patch
enables vblank interrupt on ironlake and follows vblank get/put
model.
Signed-off-by: Li Peng <peng.li@intel.com>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 30 |
1 files changed, 19 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 89a071a3e6fb..e7472d82132a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -309,6 +309,12 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
309 | if (de_iir & DE_GSE) | 309 | if (de_iir & DE_GSE) |
310 | ironlake_opregion_gse_intr(dev); | 310 | ironlake_opregion_gse_intr(dev); |
311 | 311 | ||
312 | if (de_iir & DE_PIPEA_VBLANK) | ||
313 | drm_handle_vblank(dev, 0); | ||
314 | |||
315 | if (de_iir & DE_PIPEB_VBLANK) | ||
316 | drm_handle_vblank(dev, 1); | ||
317 | |||
312 | /* check event from PCH */ | 318 | /* check event from PCH */ |
313 | if ((de_iir & DE_PCH_EVENT) && | 319 | if ((de_iir & DE_PCH_EVENT) && |
314 | (pch_iir & SDE_HOTPLUG_MASK)) { | 320 | (pch_iir & SDE_HOTPLUG_MASK)) { |
@@ -844,11 +850,11 @@ int i915_enable_vblank(struct drm_device *dev, int pipe) | |||
844 | if (!(pipeconf & PIPEACONF_ENABLE)) | 850 | if (!(pipeconf & PIPEACONF_ENABLE)) |
845 | return -EINVAL; | 851 | return -EINVAL; |
846 | 852 | ||
847 | if (IS_IRONLAKE(dev)) | ||
848 | return 0; | ||
849 | |||
850 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 853 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
851 | if (IS_I965G(dev)) | 854 | if (IS_IRONLAKE(dev)) |
855 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | ||
856 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | ||
857 | else if (IS_I965G(dev)) | ||
852 | i915_enable_pipestat(dev_priv, pipe, | 858 | i915_enable_pipestat(dev_priv, pipe, |
853 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | 859 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
854 | else | 860 | else |
@@ -866,13 +872,14 @@ void i915_disable_vblank(struct drm_device *dev, int pipe) | |||
866 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 872 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
867 | unsigned long irqflags; | 873 | unsigned long irqflags; |
868 | 874 | ||
869 | if (IS_IRONLAKE(dev)) | ||
870 | return; | ||
871 | |||
872 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 875 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
873 | i915_disable_pipestat(dev_priv, pipe, | 876 | if (IS_IRONLAKE(dev)) |
874 | PIPE_VBLANK_INTERRUPT_ENABLE | | 877 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
875 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | 878 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
879 | else | ||
880 | i915_disable_pipestat(dev_priv, pipe, | ||
881 | PIPE_VBLANK_INTERRUPT_ENABLE | | ||
882 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | ||
876 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | 883 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
877 | } | 884 | } |
878 | 885 | ||
@@ -1015,7 +1022,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1015 | { | 1022 | { |
1016 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1023 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1017 | /* enable kind of interrupts always enabled */ | 1024 | /* enable kind of interrupts always enabled */ |
1018 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; | 1025 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1026 | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; | ||
1019 | u32 render_mask = GT_USER_INTERRUPT; | 1027 | u32 render_mask = GT_USER_INTERRUPT; |
1020 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | 1028 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1021 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | 1029 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |