diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-21 06:19:32 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-21 06:19:32 -0400 |
commit | e9e5f8e8d373e72f5c39dafde1ce110fc7082118 (patch) | |
tree | 2991e33571a59cc2488daef36dcfeab7bddb9d7f /drivers/gpu/drm/i915/i915_gem.c | |
parent | f899fc64cda8569d0529452aafc0da31c042df2e (diff) | |
parent | db8c076b9206ea35b1f7299708d5510b17674db2 (diff) |
Merge branch 'drm-intel-fixes' into HEAD
Conflicts:
drivers/char/agp/intel-agp.c
drivers/gpu/drm/i915/intel_crt.c
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 37 |
1 files changed, 24 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a83574df096e..0355cd28b270 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -2350,14 +2350,21 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, | |||
2350 | 2350 | ||
2351 | reg->obj = obj; | 2351 | reg->obj = obj; |
2352 | 2352 | ||
2353 | if (IS_GEN6(dev)) | 2353 | switch (INTEL_INFO(dev)->gen) { |
2354 | case 6: | ||
2354 | sandybridge_write_fence_reg(reg); | 2355 | sandybridge_write_fence_reg(reg); |
2355 | else if (IS_I965G(dev)) | 2356 | break; |
2357 | case 5: | ||
2358 | case 4: | ||
2356 | i965_write_fence_reg(reg); | 2359 | i965_write_fence_reg(reg); |
2357 | else if (IS_I9XX(dev)) | 2360 | break; |
2361 | case 3: | ||
2358 | i915_write_fence_reg(reg); | 2362 | i915_write_fence_reg(reg); |
2359 | else | 2363 | break; |
2364 | case 2: | ||
2360 | i830_write_fence_reg(reg); | 2365 | i830_write_fence_reg(reg); |
2366 | break; | ||
2367 | } | ||
2361 | 2368 | ||
2362 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, | 2369 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2363 | obj_priv->tiling_mode); | 2370 | obj_priv->tiling_mode); |
@@ -2380,22 +2387,26 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |||
2380 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | 2387 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
2381 | struct drm_i915_fence_reg *reg = | 2388 | struct drm_i915_fence_reg *reg = |
2382 | &dev_priv->fence_regs[obj_priv->fence_reg]; | 2389 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
2390 | uint32_t fence_reg; | ||
2383 | 2391 | ||
2384 | if (IS_GEN6(dev)) { | 2392 | switch (INTEL_INFO(dev)->gen) { |
2393 | case 6: | ||
2385 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | 2394 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2386 | (obj_priv->fence_reg * 8), 0); | 2395 | (obj_priv->fence_reg * 8), 0); |
2387 | } else if (IS_I965G(dev)) { | 2396 | break; |
2397 | case 5: | ||
2398 | case 4: | ||
2388 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | 2399 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
2389 | } else { | 2400 | break; |
2390 | uint32_t fence_reg; | 2401 | case 3: |
2391 | 2402 | if (obj_priv->fence_reg > 8) | |
2392 | if (obj_priv->fence_reg < 8) | 2403 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
2393 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | ||
2394 | else | 2404 | else |
2395 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | 2405 | case 2: |
2396 | 8) * 4; | 2406 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
2397 | 2407 | ||
2398 | I915_WRITE(fence_reg, 0); | 2408 | I915_WRITE(fence_reg, 0); |
2409 | break; | ||
2399 | } | 2410 | } |
2400 | 2411 | ||
2401 | reg->obj = NULL; | 2412 | reg->obj = NULL; |