drm/i915: merge get_gtt_alignment/get_unfenced_gtt_alignment()

The two functions are rather similar, so merge them.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 37 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e6cc020ea32c..2166b61053c6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1463,16 +1463,15 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
  * Return the required GTT alignment for an object, taking into account
  * potential fence register mapping.
  */
-static uint32_t
-i915_gem_get_gtt_alignment(struct drm_device *dev,
-                           uint32_t size,
-                           int tiling_mode)
+uint32_t
+i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
+                           int tiling_mode, bool fenced)
 {
         /*
          * Minimum alignment is 4k (GTT page size), but might be greater
          * if a fence register is needed for the object.
          */
-        if (INTEL_INFO(dev)->gen >= 4 ||
+        if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
             tiling_mode == I915_TILING_NONE)
                 return 4096;
 
@@ -1483,35 +1482,6 @@ i915_gem_get_gtt_alignment(struct drm_device *dev,
         return i915_gem_get_gtt_size(dev, size, tiling_mode);
 }
 
-/**
- * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
- *                                       unfenced object
- * @dev: the device
- * @size: size of the object
- * @tiling_mode: tiling mode of the object
- *
- * Return the required GTT alignment for an object, only taking into account
- * unfenced tiled surface requirements.
- */
-uint32_t
-i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
-                                    uint32_t size,
-                                    int tiling_mode)
-{
-        /*
-         * Minimum alignment is 4k (GTT page size) for sane hw.
-         */
-        if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
-            tiling_mode == I915_TILING_NONE)
-                return 4096;
-
-        /* Previous hardware however needs to be aligned to a power-of-two
-         * tile height. The simplest method for determining this is to reuse
-         * the power-of-tile object size.
-         */
-        return i915_gem_get_gtt_size(dev, size, tiling_mode);
-}
-
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
 {
         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
@@ -2934,11 +2904,11 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
                                            obj->tiling_mode);
         fence_alignment = i915_gem_get_gtt_alignment(dev,
                                                      obj->base.size,
-                                                     obj->tiling_mode);
+                                                     obj->tiling_mode, true);
         unfenced_alignment =
-                i915_gem_get_unfenced_gtt_alignment(dev,
+                i915_gem_get_gtt_alignment(dev,
                                                     obj->base.size,
-                                                    obj->tiling_mode);
+                                                    obj->tiling_mode, false);
 
         if (alignment == 0)
                 alignment = map_and_fenceable ? fence_alignment :