drm/i915: set w/a bit for snb pagefaults

Bspec says that we need to set this: vol1c.3 "Blitter Command
Streamer", Section 1.1.2.1 "GAB_CTL_REG - GAB Unit Control Register".

We don't really rely on pagefaults, but who knows what this all
affects.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ac8bc1df7c8f..92acc5f8e334 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3669,7 +3669,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
         pd_offset <<= 16;
 
         if (INTEL_INFO(dev)->gen == 6) {
-                uint32_t ecochk = I915_READ(GAM_ECOCHK);
+                uint32_t ecochk, gab_ctl;
+
+                gab_ctl = I915_READ(GAB_CTL);
+                I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
+
+                ecochk = I915_READ(GAM_ECOCHK);
                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
                                        ECOCHK_PPGTT_CACHE64B);
                 I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE));