diff options
author | Eric Anholt <eric@anholt.net> | 2011-03-29 19:59:55 -0400 |
---|---|---|
committer | Keith Packard <keithp@keithp.com> | 2011-06-10 00:51:22 -0400 |
commit | a18711120764dd96ed2ee6a4d436c448542bad77 (patch) | |
tree | 1489513e3fa18f9f164ae431120d6abf62b3b276 /drivers/gpu/drm/i915/i915_gem.c | |
parent | a7ef0640d984e265393a76aa08a09febd3e7ce34 (diff) |
drm/i915: Use the LLC mode on gen6 for everything but display.
Improves full-screen openarena on my laptop 20.3% +/- 4.0% (n=3)
Improves 800x600 nexuiz on my laptop 12.3% +/- 0.1% (n=3)
We have more room to improve with doing LLC caching for display using
GFDT, and in doing LLC+MLC caching, but this was an easy performance
win and incremental improvement toward those two.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fb0538358c34..cb1f61dba5eb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -3700,7 +3700,23 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, | |||
3700 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | 3700 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3701 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | 3701 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3702 | 3702 | ||
3703 | obj->cache_level = I915_CACHE_NONE; | 3703 | if (IS_GEN6(dev)) { |
3704 | /* On Gen6, we can have the GPU use the LLC (the CPU | ||
3705 | * cache) for about a 10% performance improvement | ||
3706 | * compared to uncached. Graphics requests other than | ||
3707 | * display scanout are coherent with the CPU in | ||
3708 | * accessing this cache. This means in this mode we | ||
3709 | * don't need to clflush on the CPU side, and on the | ||
3710 | * GPU side we only need to flush internal caches to | ||
3711 | * get data visible to the CPU. | ||
3712 | * | ||
3713 | * However, we maintain the display planes as UC, and so | ||
3714 | * need to rebind when first used as such. | ||
3715 | */ | ||
3716 | obj->cache_level = I915_CACHE_LLC; | ||
3717 | } else | ||
3718 | obj->cache_level = I915_CACHE_NONE; | ||
3719 | |||
3704 | obj->base.driver_private = NULL; | 3720 | obj->base.driver_private = NULL; |
3705 | obj->fence_reg = I915_FENCE_REG_NONE; | 3721 | obj->fence_reg = I915_FENCE_REG_NONE; |
3706 | INIT_LIST_HEAD(&obj->mm_list); | 3722 | INIT_LIST_HEAD(&obj->mm_list); |