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authorAndi Kleen <ak@linux.intel.com>2011-10-13 19:08:51 -0400
committerKeith Packard <keithp@keithp.com>2011-10-21 02:21:58 -0400
commitf700088333c5c7e5a7f4ab71b642362290259e26 (patch)
treef934ef5ee960e0aecfb796b71ad054ef01b7da2d /drivers/gpu/drm/i915/i915_drv.h
parenta487928908226df493a3ce145ecf4bb39296714e (diff)
i915: Move i915_read/write out of line
With the tracing code in there they are far too big to inline. .text savings compared to a non force inline kernel: i915_restore_display 4393 12036 +7643 i915_save_display 4295 11459 +7164 i915_handle_error 2979 6666 +3687 i915_driver_irq_handler 2923 5086 +2163 i915_ringbuffer_info 458 1661 +1203 i915_save_vga - 1200 +1200 i915_driver_irq_uninstall 453 1624 +1171 i915_driver_irq_postinstall 913 2078 +1165 ironlake_enable_drps 719 1872 +1153 i915_restore_vga - 1142 +1142 intel_display_capture_error_state 784 2030 +1246 intel_init_emon 719 2016 +1297 and more ... [AK: these are older numbers, with the new SNB forcewake checks it will be even worse] Signed-off-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h22
1 files changed, 3 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c5ca0d37f089..06a37f4fd74b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1355,18 +1355,7 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1355 ((reg) != FORCEWAKE)) 1355 ((reg) != FORCEWAKE))
1356 1356
1357#define __i915_read(x, y) \ 1357#define __i915_read(x, y) \
1358static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1358 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1359 u##x val = 0; \
1360 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1361 gen6_gt_force_wake_get(dev_priv); \
1362 val = read##y(dev_priv->regs + reg); \
1363 gen6_gt_force_wake_put(dev_priv); \
1364 } else { \
1365 val = read##y(dev_priv->regs + reg); \
1366 } \
1367 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1368 return val; \
1369}
1370 1359
1371__i915_read(8, b) 1360__i915_read(8, b)
1372__i915_read(16, w) 1361__i915_read(16, w)
@@ -1375,13 +1364,8 @@ __i915_read(64, q)
1375#undef __i915_read 1364#undef __i915_read
1376 1365
1377#define __i915_write(x, y) \ 1366#define __i915_write(x, y) \
1378static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 1367 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1379 trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 1368
1380 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1381 __gen6_gt_wait_for_fifo(dev_priv); \
1382 } \
1383 write##y(val, dev_priv->regs + reg); \
1384}
1385__i915_write(8, b) 1369__i915_write(8, b)
1386__i915_write(16, w) 1370__i915_write(16, w)
1387__i915_write(32, l) 1371__i915_write(32, l)