drm/i915: move find_pll callback to dev_priv->display

Now that the DP madness is cleared out, this is all only per-platform.
So move it out from the intel clock limits structure.

While at it drop the intel prefix on the static functions, call the
vtable entry find_dpll (since it's for the display pll) and rip out
the now unnecessary forward declarations.

Note that the parameters of ->find_dpll are still unchanged, but they
eventually need to be moved over to just take in a pipe configuration.
But currently a lot of things are still missing from the pipe
configuration (reflock, output-specific dpll limits and preferences,
downclocked dotclock). So this will happen in a later step.

Note that intel_g4x_limit has a peculiar case where it selects
intel_limits_i9xx_sdvo as the limit. This is pretty bogus and also not
used since the only output types left are DP and native TV-out which
both use special pre-tuned dpll values.

v2: Re-add comment for the find_pll callback (requested by Paulo) and
elaborate on why the transformation is correct for g4x platforms (to
clarify a review question from Paulo). Double up on that by adding a
WARN as suggested by Paulo Zanoni on irc.

v3: Initialize limits to NULL since gcc is now unhappy.

v4: v2/3 will blow up with a NULL dereference in ->find_dpll for dp and
TV-out ports, spotted by Paulo on irc. So just give up on this madness for
now, and leave this to be fixed in a later patch.

v5: Since the ever-so-slight change for g4x might result in some dpll
parameter computation failing spuriously where before it didn't for
ports with preset dpll settings (DP & TV-out) override this. For
paranoia also do it in the ilk+ code.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 20 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d86ce578384..215aa63e3f47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -306,6 +306,8 @@ struct drm_i915_error_state {
 
 struct intel_crtc_config;
 struct intel_crtc;
+struct intel_limit;
+struct dpll;
 
 struct drm_i915_display_funcs {
         bool (*fbc_enabled)(struct drm_device *dev);
@@ -313,6 +315,24 @@ struct drm_i915_display_funcs {
         void (*disable_fbc)(struct drm_device *dev);
         int (*get_display_clock_speed)(struct drm_device *dev);
         int (*get_fifo_size)(struct drm_device *dev, int plane);
+        /**
+         * find_dpll() - Find the best values for the PLL
+         * @limit: limits for the PLL
+         * @crtc: current CRTC
+         * @target: target frequency in kHz
+         * @refclk: reference clock frequency in kHz
+         * @match_clock: if provided, @best_clock P divider must
+         *               match the P divider from @match_clock
+         *               used for LVDS downclocking
+         * @best_clock: best PLL values found
+         *
+         * Returns true on success, false on failure.
+         */
+        bool (*find_dpll)(const struct intel_limit *limit,
+                          struct drm_crtc *crtc,
+                          int target, int refclk,
+                          struct dpll *match_clock,
+                          struct dpll *best_clock);
         void (*update_wm)(struct drm_device *dev);
         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
                                  uint32_t sprite_width, int pixel_size,