diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2009-09-10 18:28:06 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-09-10 22:46:07 -0400 |
commit | 8082400327d8d2ca54254b593644942bed0edd25 (patch) | |
tree | 43a32ac4e56e985341e2109d2c4d545d3d6df6cb /drivers/gpu/drm/i915/i915_drv.h | |
parent | 06324194eee97a51b5f172270df49ec39192d6cc (diff) |
drm/i915: framebuffer compression for pre-GM45
This patch adds framebuffer compression (good for about ~0.5W power
savings in the best case) support for pre-GM45 chips. GM45+ have a new,
more flexible FBC scheme that will be added in a separate patch.
FBC can't always be enabled: the compressed buffer must be physically
contiguous and reside in stolen space. So if you have a large display
and a small amount of stolen memory, you may not be able to take
advantage of FBC. In some cases, a BIOS setting controls how much
stolen space is available. Increasing this to 8 or 16M can help.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f2b8d27aef2a..0344afd841c4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -48,6 +48,11 @@ enum pipe { | |||
48 | PIPE_B, | 48 | PIPE_B, |
49 | }; | 49 | }; |
50 | 50 | ||
51 | enum plane { | ||
52 | PLANE_A = 0, | ||
53 | PLANE_B, | ||
54 | }; | ||
55 | |||
51 | #define I915_NUM_PIPE 2 | 56 | #define I915_NUM_PIPE 2 |
52 | 57 | ||
53 | /* Interface history: | 58 | /* Interface history: |
@@ -202,6 +207,11 @@ typedef struct drm_i915_private { | |||
202 | 207 | ||
203 | struct drm_mm vram; | 208 | struct drm_mm vram; |
204 | 209 | ||
210 | unsigned long cfb_size; | ||
211 | unsigned long cfb_pitch; | ||
212 | int cfb_fence; | ||
213 | int cfb_plane; | ||
214 | |||
205 | int irq_enabled; | 215 | int irq_enabled; |
206 | 216 | ||
207 | struct intel_opregion opregion; | 217 | struct intel_opregion opregion; |
@@ -768,6 +778,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; } | |||
768 | /* modesetting */ | 778 | /* modesetting */ |
769 | extern void intel_modeset_init(struct drm_device *dev); | 779 | extern void intel_modeset_init(struct drm_device *dev); |
770 | extern void intel_modeset_cleanup(struct drm_device *dev); | 780 | extern void intel_modeset_cleanup(struct drm_device *dev); |
781 | extern void i8xx_disable_fbc(struct drm_device *dev); | ||
771 | 782 | ||
772 | /** | 783 | /** |
773 | * Lock test for when it's just for synchronization of ring access. | 784 | * Lock test for when it's just for synchronization of ring access. |
@@ -918,6 +929,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
918 | 929 | ||
919 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) | 930 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) |
920 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) | 931 | #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) |
932 | #define I915_HAS_FBC(dev) (IS_I9XX(dev) || IS_I965G(dev)) | ||
921 | 933 | ||
922 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) | 934 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
923 | 935 | ||