drm/i915: metadata for shared dplls

An id to match the idx (useful for register access macros) and a name
fore neater debug output.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 11 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d83c80a9c0b9..0fc8d616cefb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -132,23 +132,26 @@ enum hpd_pin {
         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
                 if ((intel_encoder)->base.crtc == (__crtc))
 
+enum intel_dpll_id {
+        DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
+        /* real shared dpll ids must be >= 0 */
+        DPLL_ID_PCH_PLL_A,
+        DPLL_ID_PCH_PLL_B,
+};
+#define I915_NUM_PLLS 2
+
 struct intel_shared_dpll {
         int refcount; /* count of number of CRTCs sharing this PLL */
         int active; /* count of number of active CRTCs (i.e. DPMS on) */
         bool on; /* is the PLL actually active? Disabled during modeset */
+        const char *name;
+        /* should match the index in the dev_priv->shared_dplls array */
+        enum intel_dpll_id id;
         int pll_reg;
         int fp0_reg;
         int fp1_reg;
 };
 
-enum intel_dpll_id {
-        DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
-        /* real shared dpll ids must be >= 0 */
-        DPLL_ID_PCH_PLL_A,
-        DPLL_ID_PCH_PLL_B,
-};
-#define I915_NUM_PLLS 2
-
 /* Used by dp and fdi links */
 struct intel_link_m_n {
         uint32_t        tu;