Drivers: i915: Fix all space related issues.

Various issues involved with the space character were generating
warnings in the checkpatch.pl file. This patch removes most of those
warnings.

Signed-off-by: Akshay Joshi <me@akshayjoshi.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

1 files changed, 35 insertions, 35 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7916bd97d5c1..32de06f0b172 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -226,26 +226,26 @@ struct drm_i915_display_funcs {
 
 struct intel_device_info {
         u8 gen;
-        u8 is_mobile : 1;
-        u8 is_i85x : 1;
-        u8 is_i915g : 1;
-        u8 is_i945gm : 1;
-        u8 is_g33 : 1;
-        u8 need_gfx_hws : 1;
-        u8 is_g4x : 1;
-        u8 is_pineview : 1;
-        u8 is_broadwater : 1;
-        u8 is_crestline : 1;
-        u8 is_ivybridge : 1;
-        u8 has_fbc : 1;
-        u8 has_pipe_cxsr : 1;
-        u8 has_hotplug : 1;
-        u8 cursor_needs_physical : 1;
-        u8 has_overlay : 1;
-        u8 overlay_needs_physical : 1;
-        u8 supports_tv : 1;
-        u8 has_bsd_ring : 1;
-        u8 has_blt_ring : 1;
+        u8 is_mobile:1;
+        u8 is_i85x:1;
+        u8 is_i915g:1;
+        u8 is_i945gm:1;
+        u8 is_g33:1;
+        u8 need_gfx_hws:1;
+        u8 is_g4x:1;
+        u8 is_pineview:1;
+        u8 is_broadwater:1;
+        u8 is_crestline:1;
+        u8 is_ivybridge:1;
+        u8 has_fbc:1;
+        u8 has_pipe_cxsr:1;
+        u8 has_hotplug:1;
+        u8 cursor_needs_physical:1;
+        u8 has_overlay:1;
+        u8 overlay_needs_physical:1;
+        u8 supports_tv:1;
+        u8 has_bsd_ring:1;
+        u8 has_blt_ring:1;
 };
 
 enum no_fbc_reason {
@@ -759,19 +759,19 @@ struct drm_i915_gem_object {
          * (has pending rendering), and is not set if it's on inactive (ready
          * to be unbound).
          */
-        unsigned int active : 1;
+        unsigned int active:1;
 
         /**
          * This is set if the object has been written to since last bound
          * to the GTT
          */
-        unsigned int dirty : 1;
+        unsigned int dirty:1;
 
         /**
          * This is set if the object has been written to since the last
          * GPU flush.
          */
-        unsigned int pending_gpu_write : 1;
+        unsigned int pending_gpu_write:1;
 
         /**
          * Fence register bits (if any) for this object.  Will be set
@@ -780,18 +780,18 @@ struct drm_i915_gem_object {
          *
          * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
          */
-        signed int fence_reg : 5;
+        signed int fence_reg:5;
 
         /**
          * Advice: are the backing pages purgeable?
          */
-        unsigned int madv : 2;
+        unsigned int madv:2;
 
         /**
          * Current tiling mode for the object.
          */
-        unsigned int tiling_mode : 2;
-        unsigned int tiling_changed : 1;
+        unsigned int tiling_mode:2;
+        unsigned int tiling_changed:1;
 
         /** How many users have pinned this object in GTT space. The following
          * users can each hold at most one reference: pwrite/pread, pin_ioctl
@@ -802,22 +802,22 @@ struct drm_i915_gem_object {
          *
          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
          * bits with absolutely no headroom. So use 4 bits. */
-        unsigned int pin_count : 4;
+        unsigned int pin_count:4;
 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 
         /**
          * Is the object at the current location in the gtt mappable and
          * fenceable? Used to avoid costly recalculations.
          */
-        unsigned int map_and_fenceable : 1;
+        unsigned int map_and_fenceable:1;
 
         /**
          * Whether the current gtt mapping needs to be mappable (and isn't just
          * mappable by accident). Track pin and fault separate for a more
          * accurate mappable working set.
          */
-        unsigned int fault_mappable : 1;
-        unsigned int pin_mappable : 1;
+        unsigned int fault_mappable:1;
+        unsigned int pin_mappable:1;
 
         /*
          * Is the GPU currently using a fence to access this buffer,
@@ -1056,7 +1056,7 @@ i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 void
 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 
-void intel_enable_asle (struct drm_device *dev);
+void intel_enable_asle(struct drm_device *dev);
 
 #ifdef CONFIG_DEBUG_FS
 extern void i915_destroy_error_state(struct drm_device *dev);
@@ -1146,7 +1146,7 @@ int i915_gem_dumb_create(struct drm_file *file_priv,
 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
                       uint32_t handle, uint64_t *offset);
 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
-                          uint32_t handle);                       
+                          uint32_t handle);
 /**
  * Returns true if seq1 is later than seq2.
  */
@@ -1303,8 +1303,8 @@ extern void intel_disable_fbc(struct drm_device *dev);
 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void ironlake_enable_rc6(struct drm_device *dev);
 extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void intel_detect_pch (struct drm_device *dev);
-extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
+extern void intel_detect_pch(struct drm_device *dev);
+extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
 
 /* overlay */
 #ifdef CONFIG_DEBUG_FS