drm/i915: Reorganize display pipe register accesses

RFCv2: Reorganize array indexing so that full offsets can be used as
is. It makes grepping for registers in i915_reg.h much easier. Also
move offset arrays to intel_device_info.

v1: Fixed offsets for VLV, proper eDP handling

v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros.

v3: Added EDP pipe comment, removed redundant offset arrays for
    MSA_MISC and DDI_FUNC_CTL.

v4: Rename patch and report object size increase.

v5: Change location of commas, add PIPE_EDP into enum pipe

v6: Insert PIPE_EDP_OFFSET into pipe offset array

v7: Set I915_MAX_PIPES back to 3, change more registers accessors
    to use the new macros, get rid of _PIPE_INC and add dev_priv
    as a parameter where required by the new macros.

Upcoming hardware will not have the various display pipe register
ranges evenly spaced in memory. Change register address calculations
into array lookups.

Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP.

I left the UMS cruft untouched.

Size differences:
   text    data     bss     dec     hex filename
 596431    4634      56  601121   92c21 i915.ko (new)
 593199    4634      56  597889   91f81 i915.ko (old)

Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 10 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e908c9910640..728b9c3f0421 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,7 +58,8 @@ enum pipe {
         PIPE_A = 0,
         PIPE_B,
         PIPE_C,
-        I915_MAX_PIPES
+        _PIPE_EDP,
+        I915_MAX_PIPES = _PIPE_EDP
 };
 #define pipe_name(p) ((p) + 'A')
 
@@ -66,7 +67,8 @@ enum transcoder {
         TRANSCODER_A = 0,
         TRANSCODER_B,
         TRANSCODER_C,
-        TRANSCODER_EDP = 0xF,
+        TRANSCODER_EDP,
+        I915_MAX_TRANSCODERS
 };
 #define transcoder_name(t) ((t) + 'A')
 
@@ -531,6 +533,12 @@ struct intel_device_info {
         u8 gen;
         u8 ring_mask; /* Rings supported by the HW */
         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+        /* Register offsets for the various display pipes and transcoders */
+        int pipe_offsets[I915_MAX_TRANSCODERS];
+        int trans_offsets[I915_MAX_TRANSCODERS];
+        int dpll_offsets[I915_MAX_PIPES];
+        int dpll_md_offsets[I915_MAX_PIPES];
+        int palette_offsets[I915_MAX_PIPES];
 };
 
 #undef DEFINE_FLAG