drm/i915: Modifying structures related to DRRS

Earlier, DRRS structures were specific to eDP (used only in intel_dp).
Since DRRS can be extended to other internal display types
(if the panel supports multiple RR), modifying structures
to be part of drm_i915_private and have a provision to add display related
structs like intel_dp.
Also, aligning with frontbuffer tracking mechanism, the new structure
contains data for busy frontbuffer bits.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 24 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5616471f45d..2d3355aa17ac 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,11 +777,33 @@ struct i915_fbc {
         } no_fbc_reason;
 };
 
-struct i915_drrs {
-        struct intel_connector *connector;
+/**
+ * HIGH_RR is the highest eDP panel refresh rate read from EDID
+ * LOW_RR is the lowest eDP panel refresh rate found from EDID
+ * parsing for same resolution.
+ */
+enum drrs_refresh_rate_type {
+        DRRS_HIGH_RR,
+        DRRS_LOW_RR,
+        DRRS_MAX_RR, /* RR count */
+};
+
+enum drrs_support_type {
+        DRRS_NOT_SUPPORTED = 0,
+        STATIC_DRRS_SUPPORT = 1,
+        SEAMLESS_DRRS_SUPPORT = 2
 };
 
 struct intel_dp;
+struct i915_drrs {
+        struct mutex mutex;
+        struct delayed_work work;
+        struct intel_dp *dp;
+        unsigned busy_frontbuffer_bits;
+        enum drrs_refresh_rate_type refresh_rate_type;
+        enum drrs_support_type type;
+};
+
 struct i915_psr {
         struct mutex lock;
         bool sink_support;
@@ -1361,12 +1383,6 @@ struct ddi_vbt_port_info {
         uint8_t supports_dp:1;
 };
 
-enum drrs_support_type {
-        DRRS_NOT_SUPPORTED = 0,
-        STATIC_DRRS_SUPPORT = 1,
-        SEAMLESS_DRRS_SUPPORT = 2
-};
-
 enum psr_lines_to_wait {
         PSR_0_LINES_TO_WAIT = 0,
         PSR_1_LINE_TO_WAIT,