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authorEric Anholt <eric@anholt.net>2009-10-22 19:11:14 -0400
committerEric Anholt <eric@anholt.net>2010-02-26 16:23:17 -0500
commitbad720ff3e8e47a04bd88d9bbc8317e7d7e049d3 (patch)
treef799c660fbe0530398366f46da0fb25381b78978 /drivers/gpu/drm/i915/i915_drv.h
parent1089e3009572e07a1fe12c3408828f27c96453be (diff)
drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h26
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ec06d4865a5f..f97592609da4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1065,7 +1065,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1065#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1065#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1066#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 1066#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1067#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1067#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1068#define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx) 1068#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1069#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1069#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1070#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1070#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1071#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1071#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
@@ -1084,8 +1084,29 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1084#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) 1084#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1085#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1085#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1086 1086
1087#define IS_GEN3(dev) (IS_I915G(dev) || \
1088 IS_I915GM(dev) || \
1089 IS_I945G(dev) || \
1090 IS_I945GM(dev) || \
1091 IS_G33(dev) || \
1092 IS_PINEVIEW(dev))
1093#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1094 (dev)->pci_device == 0x2982 || \
1095 (dev)->pci_device == 0x2992 || \
1096 (dev)->pci_device == 0x29A2 || \
1097 (dev)->pci_device == 0x2A02 || \
1098 (dev)->pci_device == 0x2A12 || \
1099 (dev)->pci_device == 0x2E02 || \
1100 (dev)->pci_device == 0x2E12 || \
1101 (dev)->pci_device == 0x2E22 || \
1102 (dev)->pci_device == 0x2E32 || \
1103 (dev)->pci_device == 0x2A42 || \
1104 (dev)->pci_device == 0x2E42)
1105
1087#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1106#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1088 1107
1108#define IS_GEN6(dev) ((dev)->pci_device == 0x0102)
1109
1089/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1110/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1090 * rows, which changed the alignment requirements and fence programming. 1111 * rows, which changed the alignment requirements and fence programming.
1091 */ 1112 */
@@ -1106,6 +1127,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1106#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1127#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1107#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) 1128#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1108 1129
1130#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1131 IS_GEN6(dev))
1132
1109#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1133#define PRIMARY_RINGBUFFER_SIZE (128*1024)
1110 1134
1111#endif 1135#endif