drm/i915: Use 128k alignment for untiled display surface on i965 (v2)

The original i965, including the revised G35 and Q35, requires an
alignment of 128K for the display surface with linear memory, so
increase the requirement from 64k for these chipsets. For the later
chipsets in the i965 family, only a 4k alignment is required. (So
long as we do not start performing asynchronous flips.)

Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.

v2: compilation fixes and note that the docs do not exclude the G35 from
the extra alignment.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 70e252768ab3..5a0100ef21d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -201,6 +201,8 @@ struct intel_device_info {
         u8 need_gfx_hws : 1;
         u8 is_g4x : 1;
         u8 is_pineview : 1;
+        u8 is_broadwater : 1;
+        u8 is_crestline : 1;
         u8 is_ironlake : 1;
         u8 is_gen6 : 1;
         u8 has_fbc : 1;
@@ -1134,6 +1136,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 #define IS_I965G(dev)           (INTEL_INFO(dev)->is_i965g)
 #define IS_I965GM(dev)          (INTEL_INFO(dev)->is_i965gm)
+#define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
+#define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)