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author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-25 03:41:59 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-25 09:18:41 -0400 |
commit | cb54b53adae70701bdd77d848cea4b9b39b61cf9 (patch) | |
tree | b9da2ccaf8b2207fd4e9f7ca1905a4500e011731 /drivers/gpu/drm/i915/i915_drv.c | |
parent | d861e3387650296f1fca2a4dd0dcd380c8fdddad (diff) | |
parent | 549f3a1218ba18fcde11ef0e22b07e6365645788 (diff) |
Merge commit 'Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux'
This backmerges Linus' merge commit of the latest drm-fixes pull:
commit 549f3a1218ba18fcde11ef0e22b07e6365645788
Merge: 42577ca 058ca4a
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Tue Jul 23 15:47:08 2013 -0700
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
We've accrued a few too many conflicts, but the real reason is that I
want to merge the 100% solution for Haswell concurrent registers
writes into drm-intel-next. But that depends upon the 90% bandaid
merged into -fixes:
commit a7cd1b8fea2f341b626b255d9898a5ca5fabbf0a
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 19 20:36:51 2013 +0100
drm/i915: Serialize almost all register access
Also, we can roll up on accrued conflicts.
Usually I'd backmerge a tagged -rc, but I want to get this done before
heading off to vacations next week ;-)
Conflicts:
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_gem.c
v2: For added hilarity we have a init sequence conflict around the
gt_lock, so need to move that one, too. Spotted by Jani Nikula.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index c34086ad8181..5849b0a91b4e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -127,10 +127,10 @@ module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 060 | |||
127 | MODULE_PARM_DESC(preliminary_hw_support, | 127 | MODULE_PARM_DESC(preliminary_hw_support, |
128 | "Enable preliminary hardware support. (default: false)"); | 128 | "Enable preliminary hardware support. (default: false)"); |
129 | 129 | ||
130 | int i915_disable_power_well __read_mostly = 0; | 130 | int i915_disable_power_well __read_mostly = 1; |
131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); | 131 | module_param_named(disable_power_well, i915_disable_power_well, int, 0600); |
132 | MODULE_PARM_DESC(disable_power_well, | 132 | MODULE_PARM_DESC(disable_power_well, |
133 | "Disable the power well when possible (default: false)"); | 133 | "Disable the power well when possible (default: true)"); |
134 | 134 | ||
135 | int i915_enable_ips __read_mostly = 1; | 135 | int i915_enable_ips __read_mostly = 1; |
136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); | 136 | module_param_named(enable_ips, i915_enable_ips, int, 0600); |
@@ -723,7 +723,7 @@ static int i915_drm_thaw(struct drm_device *dev) | |||
723 | { | 723 | { |
724 | int error = 0; | 724 | int error = 0; |
725 | 725 | ||
726 | intel_gt_reset(dev); | 726 | intel_gt_sanitize(dev); |
727 | 727 | ||
728 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | 728 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
729 | mutex_lock(&dev->struct_mutex); | 729 | mutex_lock(&dev->struct_mutex); |
@@ -749,7 +749,7 @@ int i915_resume(struct drm_device *dev) | |||
749 | 749 | ||
750 | pci_set_master(dev->pdev); | 750 | pci_set_master(dev->pdev); |
751 | 751 | ||
752 | intel_gt_reset(dev); | 752 | intel_gt_sanitize(dev); |
753 | 753 | ||
754 | /* | 754 | /* |
755 | * Platforms with opregion should have sane BIOS, older ones (gen3 and | 755 | * Platforms with opregion should have sane BIOS, older ones (gen3 and |
@@ -1271,21 +1271,21 @@ hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |||
1271 | 1271 | ||
1272 | #define __i915_read(x, y) \ | 1272 | #define __i915_read(x, y) \ |
1273 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | 1273 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ |
1274 | unsigned long irqflags; \ | ||
1274 | u##x val = 0; \ | 1275 | u##x val = 0; \ |
1276 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
1275 | if (IS_GEN5(dev_priv->dev)) \ | 1277 | if (IS_GEN5(dev_priv->dev)) \ |
1276 | ilk_dummy_write(dev_priv); \ | 1278 | ilk_dummy_write(dev_priv); \ |
1277 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | 1279 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1278 | unsigned long irqflags; \ | ||
1279 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
1280 | if (dev_priv->forcewake_count == 0) \ | 1280 | if (dev_priv->forcewake_count == 0) \ |
1281 | dev_priv->gt.force_wake_get(dev_priv); \ | 1281 | dev_priv->gt.force_wake_get(dev_priv); \ |
1282 | val = read##y(dev_priv->regs + reg); \ | 1282 | val = read##y(dev_priv->regs + reg); \ |
1283 | if (dev_priv->forcewake_count == 0) \ | 1283 | if (dev_priv->forcewake_count == 0) \ |
1284 | dev_priv->gt.force_wake_put(dev_priv); \ | 1284 | dev_priv->gt.force_wake_put(dev_priv); \ |
1285 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
1286 | } else { \ | 1285 | } else { \ |
1287 | val = read##y(dev_priv->regs + reg); \ | 1286 | val = read##y(dev_priv->regs + reg); \ |
1288 | } \ | 1287 | } \ |
1288 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
1289 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | 1289 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
1290 | return val; \ | 1290 | return val; \ |
1291 | } | 1291 | } |
@@ -1298,8 +1298,10 @@ __i915_read(64, q) | |||
1298 | 1298 | ||
1299 | #define __i915_write(x, y) \ | 1299 | #define __i915_write(x, y) \ |
1300 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | 1300 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
1301 | unsigned long irqflags; \ | ||
1301 | u32 __fifo_ret = 0; \ | 1302 | u32 __fifo_ret = 0; \ |
1302 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | 1303 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1304 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | ||
1303 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | 1305 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1304 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | 1306 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
1305 | } \ | 1307 | } \ |
@@ -1311,6 +1313,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |||
1311 | gen6_gt_check_fifodbg(dev_priv); \ | 1313 | gen6_gt_check_fifodbg(dev_priv); \ |
1312 | } \ | 1314 | } \ |
1313 | hsw_unclaimed_reg_check(dev_priv, reg); \ | 1315 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
1316 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | ||
1314 | } | 1317 | } |
1315 | __i915_write(8, b) | 1318 | __i915_write(8, b) |
1316 | __i915_write(16, w) | 1319 | __i915_write(16, w) |