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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-19 07:31:36 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 06:19:53 -0400
commit77f01230223a08792f5320ebba27af9cbb81b0cf (patch)
tree26781f9316514cabec7b8cd449827dc04cb349b1 /drivers/gpu/drm/i915/i915_drv.c
parent9375e446e7f43be9a7c21e246cee35ea912532ec (diff)
drm/i915: Clear GPU read domains on reset
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index cb1ddc6af6a6..38e889bfd99c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -391,6 +391,11 @@ int i965_reset(struct drm_device *dev, u8 flags)
391 */ 391 */
392 i915_gem_reset_flushing_list(dev); 392 i915_gem_reset_flushing_list(dev);
393 393
394 /* Move everything out of the GPU domains to ensure we do any
395 * necessary invalidation upon reuse.
396 */
397 i915_gem_reset_inactive_gpu_domains(dev);
398
394 /* 399 /*
395 * Set the domains we want to reset (GRDOM/bits 2 and 3) as 400 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
396 * well as the reset bit (GR/bit 0). Setting the GR bit 401 * well as the reset bit (GR/bit 0). Setting the GR bit