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authorChris Wilson <chris@chris-wilson.co.uk>2012-09-14 06:57:46 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-20 08:23:07 -0400
commit934d6086ea6b165af9218e8dcc2a9e69e1850743 (patch)
tree43539f5b87365c5573b6cabbfaa3a90e897c16fa /drivers/gpu/drm/i915/i915_dma.c
parentac6ae347a50bfb4667438272c0d48f4fd41154db (diff)
drm/i915: Limit the ioremap of the PCI bar to the registers
In the future we may like to experiment with using a WC map of the GTT portion. However, that will conflict with i915.ko mapping the entire bar as UC in order to access the GPU registers. Instead we can shrink the register ioremap to only map the register block. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by (IVB): Ben Widawsky <ben@bwidawsk.net> Acked-by: Ben Widawsky <ben@bwidawsk.net> [danvet: Squashed-in follow-up fix for gen2/3 registers file size from Chris Wilson.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2c09900e3267..67cdea70c561 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1461,7 +1461,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1461{ 1461{
1462 struct drm_i915_private *dev_priv; 1462 struct drm_i915_private *dev_priv;
1463 struct intel_device_info *info; 1463 struct intel_device_info *info;
1464 int ret = 0, mmio_bar; 1464 int ret = 0, mmio_bar, mmio_size;
1465 uint32_t aperture_size; 1465 uint32_t aperture_size;
1466 1466
1467 info = (struct intel_device_info *) flags; 1467 info = (struct intel_device_info *) flags;
@@ -1526,7 +1526,19 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1526 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); 1526 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1527 1527
1528 mmio_bar = IS_GEN2(dev) ? 1 : 0; 1528 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1529 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0); 1529 /* Before gen4, the registers and the GTT are behind different BARs.
1530 * However, from gen4 onwards, the registers and the GTT are shared
1531 * in the same BAR, so we want to restrict this ioremap from
1532 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1533 * the register BAR remains the same size for all the earlier
1534 * generations up to Ironlake.
1535 */
1536 if (info->gen < 5)
1537 mmio_size = 512*1024;
1538 else
1539 mmio_size = 2*1024*1024;
1540
1541 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1530 if (!dev_priv->regs) { 1542 if (!dev_priv->regs) {
1531 DRM_ERROR("failed to map registers\n"); 1543 DRM_ERROR("failed to map registers\n");
1532 ret = -EIO; 1544 ret = -EIO;