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authorChris Wilson <chris@chris-wilson.co.uk>2010-10-28 06:26:06 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-28 06:26:06 -0400
commitb4ce0f85159f77f208a62930f67b4e548576a5a3 (patch)
treeeae71707935fb4833772d539762d1cc7496b052b /drivers/gpu/drm/i915/i915_dma.c
parentf406839f094ef24bb201c9574fdb9ce8e799a975 (diff)
drm/i915: Use pci_iomap for remapping the MMIO registers.
Play safe and use the common routines which take care of the cachability of the memory when setting up the iomapping for the PCI registers. Whilst they should be cacheable for the current generations, actually honouring what the device requires is a better long term strategy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_dma.c')
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c21
1 files changed, 8 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d8def48242c8..f8827c23a668 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1888,7 +1888,6 @@ EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1888int i915_driver_load(struct drm_device *dev, unsigned long flags) 1888int i915_driver_load(struct drm_device *dev, unsigned long flags)
1889{ 1889{
1890 struct drm_i915_private *dev_priv; 1890 struct drm_i915_private *dev_priv;
1891 resource_size_t base, size;
1892 int ret = 0, mmio_bar; 1891 int ret = 0, mmio_bar;
1893 uint32_t agp_size, prealloc_size; 1892 uint32_t agp_size, prealloc_size;
1894 /* i915 has 4 more counters */ 1893 /* i915 has 4 more counters */
@@ -1906,11 +1905,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1906 dev_priv->dev = dev; 1905 dev_priv->dev = dev;
1907 dev_priv->info = (struct intel_device_info *) flags; 1906 dev_priv->info = (struct intel_device_info *) flags;
1908 1907
1909 /* Add register map (needed for suspend/resume) */
1910 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1911 base = pci_resource_start(dev->pdev, mmio_bar);
1912 size = pci_resource_len(dev->pdev, mmio_bar);
1913
1914 if (i915_get_bridge_dev(dev)) { 1908 if (i915_get_bridge_dev(dev)) {
1915 ret = -EIO; 1909 ret = -EIO;
1916 goto free_priv; 1910 goto free_priv;
@@ -1920,6 +1914,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1920 if (IS_GEN2(dev)) 1914 if (IS_GEN2(dev))
1921 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); 1915 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1922 1916
1917 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1918 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1919 if (!dev_priv->regs) {
1920 DRM_ERROR("failed to map registers\n");
1921 ret = -EIO;
1922 goto put_bridge;
1923 }
1924
1923 dev_priv->mm.gtt = intel_gtt_get(); 1925 dev_priv->mm.gtt = intel_gtt_get();
1924 if (!dev_priv->mm.gtt) { 1926 if (!dev_priv->mm.gtt) {
1925 DRM_ERROR("Failed to initialize GTT\n"); 1927 DRM_ERROR("Failed to initialize GTT\n");
@@ -1930,13 +1932,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1930 prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT; 1932 prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
1931 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 1933 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1932 1934
1933 dev_priv->regs = ioremap(base, size);
1934 if (!dev_priv->regs) {
1935 DRM_ERROR("failed to map registers\n");
1936 ret = -EIO;
1937 goto put_bridge;
1938 }
1939
1940 dev_priv->mm.gtt_mapping = 1935 dev_priv->mm.gtt_mapping =
1941 io_mapping_create_wc(dev->agp->base, agp_size); 1936 io_mapping_create_wc(dev->agp->base, agp_size);
1942 if (dev_priv->mm.gtt_mapping == NULL) { 1937 if (dev_priv->mm.gtt_mapping == NULL) {