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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-01-31 10:47:56 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-02-08 17:19:21 -0500
commit3fa7d235440a18855cfdba76d6fc788db99eac28 (patch)
treea02b5470b8034d3f9730b013051065a7534d38aa /drivers/gpu/drm/i915/i915_debugfs.c
parent11782b0233c06a35776786f30e19dc4168eb5406 (diff)
drm/i915: add gen6+ registers to i915_swizzle_info
Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 681cbe4e6e2d..4ebca6d0494f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1422,6 +1422,19 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
1422 I915_READ16(C0DRB3)); 1422 I915_READ16(C0DRB3));
1423 seq_printf(m, "C1DRB3 = 0x%04x\n", 1423 seq_printf(m, "C1DRB3 = 0x%04x\n",
1424 I915_READ16(C1DRB3)); 1424 I915_READ16(C1DRB3));
1425 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1426 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1427 I915_READ(MAD_DIMM_C0));
1428 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1429 I915_READ(MAD_DIMM_C1));
1430 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1431 I915_READ(MAD_DIMM_C2));
1432 seq_printf(m, "TILECTL = 0x%08x\n",
1433 I915_READ(TILECTL));
1434 seq_printf(m, "ARB_MODE = 0x%08x\n",
1435 I915_READ(ARB_MODE));
1436 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1437 I915_READ(DISP_ARB_CTL));
1425 } 1438 }
1426 mutex_unlock(&dev->struct_mutex); 1439 mutex_unlock(&dev->struct_mutex);
1427 1440