diff options
author | Zhao Yakui <yakui.zhao@intel.com> | 2012-08-08 09:57:01 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-08-23 19:29:31 -0400 |
commit | 9a9f5786fcccda3cc61eaa8f537690327eff6853 (patch) | |
tree | 5cd213dafb3ddb148aa339d8bdc5d27c6faa2d7d /drivers/gpu/drm/gma500 | |
parent | d112a8163f83752361dd639a9a579ae5cc05c6cf (diff) |
gma500: Disable the clock gating of display controller to make DP/eDP work well
I don't know why the DP/eDP is affected by the clock gating. But the test
shows that it really fixes the DP/eDP clock issue during enabling DP/eDP.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
[Updated to only apply the workaround if the device has DP. We don't want
to do this on netbooks]
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500')
-rw-r--r-- | drivers/gpu/drm/gma500/cdv_intel_dp.c | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/gma500/psb_intel_reg.h | 4 |
2 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c index 0571ef9b889b..9bacce3ce53c 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_dp.c +++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c | |||
@@ -1778,6 +1778,28 @@ static bool cdv_intel_dpc_is_edp(struct drm_device *dev) | |||
1778 | return false; | 1778 | return false; |
1779 | } | 1779 | } |
1780 | 1780 | ||
1781 | /* Cedarview display clock gating | ||
1782 | |||
1783 | We need this disable dot get correct behaviour while enabling | ||
1784 | DP/eDP. TODO - investigate if we can turn it back to normality | ||
1785 | after enabling */ | ||
1786 | static void cdv_disable_intel_clock_gating(struct drm_device *dev) | ||
1787 | { | ||
1788 | u32 reg_value; | ||
1789 | reg_value = REG_READ(DSPCLK_GATE_D); | ||
1790 | |||
1791 | reg_value |= (DPUNIT_PIPEB_GATE_DISABLE | | ||
1792 | DPUNIT_PIPEA_GATE_DISABLE | | ||
1793 | DPCUNIT_CLOCK_GATE_DISABLE | | ||
1794 | DPLSUNIT_CLOCK_GATE_DISABLE | | ||
1795 | DPOUNIT_CLOCK_GATE_DISABLE | | ||
1796 | DPIOUNIT_CLOCK_GATE_DISABLE); | ||
1797 | |||
1798 | REG_WRITE(DSPCLK_GATE_D, reg_value); | ||
1799 | |||
1800 | udelay(500); | ||
1801 | } | ||
1802 | |||
1781 | void | 1803 | void |
1782 | cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) | 1804 | cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) |
1783 | { | 1805 | { |
@@ -1841,6 +1863,8 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev | |||
1841 | break; | 1863 | break; |
1842 | } | 1864 | } |
1843 | 1865 | ||
1866 | cdv_disable_intel_clock_gating(dev); | ||
1867 | |||
1844 | cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name); | 1868 | cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name); |
1845 | /* FIXME:fail check */ | 1869 | /* FIXME:fail check */ |
1846 | cdv_intel_dp_add_properties(connector); | 1870 | cdv_intel_dp_add_properties(connector); |
diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h index 389e969e8986..d914719c4b60 100644 --- a/drivers/gpu/drm/gma500/psb_intel_reg.h +++ b/drivers/gpu/drm/gma500/psb_intel_reg.h | |||
@@ -1313,6 +1313,10 @@ No status bits are changed. | |||
1313 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ | 1313 | # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ |
1314 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) | 1314 | # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) |
1315 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) | 1315 | # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) |
1316 | # define DPUNIT_PIPEB_GATE_DISABLE (1 << 30) | ||
1317 | # define DPUNIT_PIPEA_GATE_DISABLE (1 << 25) | ||
1318 | # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) | ||
1319 | # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) | ||
1316 | 1320 | ||
1317 | #define RAMCLK_GATE_D 0x6210 | 1321 | #define RAMCLK_GATE_D 0x6210 |
1318 | 1322 | ||